Search

The reconstruction of 4°off 4H-SiC surfaces was investigated using Si melting at 1550°C in a SiC/Si/SiC sandwich configuration. Despite systematically obtaining a macrostepped morphology over the entire areas in contact with the liquid Si, the steps were found wavy when using as-received 4H-SiC wafers. The regularity and straightness of the steps were significantly improved when the surface reconstruction was performed on processed surfaces: on re-polished surfaces the steps were found to be regular and straight in some cases, while this was constantly observed on as-grown epitaxial layers. After a reconstruction process of 2h, the best regularity of the steps was obtained with an average width of ̴ 3-5 μm. Increasing the processed area from 1.44 to 4 cm2 did not affect the results which suggests a good scalability of the process.

Current electronics technology increasingly demands higher integration, flexibility, higher efficiency, and performance aspects such as compatibility with higher temperature operation of the semiconductor devices, which may find limitations when silicon is used. The superior intrinsic properties of SiC, eventually combined with the ability of growing monolithically epitaxial, high quality graphene on a SiC wafer (1), makes it a reliable alternative for some electronic applications, such as field effect transistors (FET), radio frequency (RF) power amplifiers, integrated circuits (IC), or sensors. In this work, we describe the fabrication and preliminary electrical characterizations of epitaxial graphene (EG) on a SiC substrate FET devices based on an alternative back gate architecture. We propose a new approach in which the FET device is built on a 4◦ off-axis cut, N+ doped 4H-SiC substrate (the back gate) with, on top of, it a 1μm semi-insulating homoepitaxial layer of SiC compensated with vanadium (the dielectric layer). EG will be used as FET conduction channel. Using this V-compensated dielectric layer is aimed to minimize effects on the FET characteristics such as from defects in the SiC crystal, especially below the FET active areas, which would have occurred when using ion implantation to create a buried gate. The EG film was grown by the high temperature Si sublimation method under an Ar ambient. Raman spectroscopy, Atomic Force Microscopy (AFM) and Scanning Electron Microscopy (SEM) were applied in the structural characterization of epigraphene. The lack of D-peak in Raman spectra, together with SEM and AFM images, indicate that high quality monolayer to few layer epitaxial graphene fully covering the SiC surface is deposited. The electrical characteristics of the EG channel-devices and the functionality of the bottom gate were examined with 2-probe and 4-probe method. The electrical properties of the FET devices were also investigated with 3 terminal configuration.

This work aims to the analysis of high-voltage (HV) SiC MOSFETs’ reliability and robustness. Large-area (up to 25 mm2) devices rated for 1.7-, 3.3-, and 4.5-kV applications were fabricated with a special process for gate oxide formation aimed to improve channel mobility. This treatment consists of the incorporation of boron atoms into the SiO2/SiC interface. The unit cell was designed to achieve a good short-circuit performance. As voltage rating increases, the reliability and robustness of power devices are crucial. Nevertheless, the procedures to test and characterize wide bandgap (WBG) power devices are still not standardized. In this work, the $V_{\mathrm {th}}$ drift was evaluated at room temperature and at high temperature using a gate stress test specific for SiC devices. Switching at high bus voltage, short-circuit and power cycling were considered as reliability tests. Test results put in evidence that fabricated devices show reasonably good robustness but suffer from a significant $V_{\mathrm {th}}$ drift caused by the boron process added to the gate oxide formation.

Owing to their low dark current, high transparency, high thermal conductivity, and potential radiation hardness, there is a special interest in silicon carbide (SiC) devices for radiation monitoring in radiation harsh environments and with elevated temperatures and, especially, for the plasma diagnostic systems in future nuclear fusion reactors. In this work, four-quadrant p-n junction diodes produced on epitaxial 4H-SiC substrates are studied. The impact of electron, neutron, and proton irradiations (up to fluences of 1 × 10 16 electrons (e)/cm 2 , 2 × 10 15 neutrons (n)/cm 2 , and 2.5 × 10 15 protons (p)/cm 2 , respectively) on the electrical characteristics is studied by means of current-voltage (I-V) and capacitance-voltage (C-V) techniques. Regardless of the particle type and applied fluences, the results show similar low reverse currents for irradiated SiC devices, which are at least about four orders of magnitude lower than comparable Si devices. The effects of irradiation on interquadrant resistance and charge build-up in the interquadrant isolation are assessed. Furthermore, device performance as a radiation detector is investigated upon exposure to a collimated 239 Pu- 241 Am- 244 Cm trialpha source. The performance at room temperature is preserved even for the highest irradiation fluences, despite the fact that the rectification character in electrical characteristics is lost. From the results, advantages of using SiC devices in alpha particle detection in harsh environments can be envisaged., This work was supported in part by the Spanish Ministry of Science, Innovation and Universities through the Nuclear and Particle Physics Program under Project FIS-FPN-RTI2018-094906-B-C22 (MCIU/FEDER UE), in part by the European Union’s Horizon 2020 Research and Innovation Program under Grant 654168 (AIDA-2020), in part by a collaborative research project at Nuclear Professional School, School of Engineering, The University of Tokyo, under Grant 20016, in part by The Japan Society for the Promotion of Science KAKNHI under Grant JP19K05337, and in part by MINECO through the use of the Spanish ICTS Network MICRONANOFABS. The work of Gemma Rius was supported by the Spanish Ministry of Science and Innovation through Ayudas Ramón y Cajal 2016 under Reference RYC-2016-21412.

Due to their low leakage current, low noise levels, high thermal conductivity, and potential radiation hardness, SiC devices offer various advantages over Si devices in certain applications. As a result, they are being considered for operation in harsh environments, such as plasma diagnostic systems in future nuclear fusion reactors or in high energy physics applications. We report on relevant results of the GRACE project, which seeks to deliver a new generation of SiC sensors with graphene-enhanced contacts. Such devices are aimed to be radiation-hard and functional at high temperatures. The work presented in this paper focuses on the optimisation of the electrical contacts, along with the electrical characterisation and radiation-tolerance assessment of the first sensor prototypes produced., This work was supported by the Spanish State Research Agency (AEI) and the European Regional Development Fund (ERDF), ref. RTC-2017-6369-3.

This paper presents a dynamic investigation of the body diode behavior of MOSFETs rated for 3.3kV applications. The body diodes of MOSFETs with different cell designs and pitch sizes have been used. The turn-off behavior of the body diode is compared to that of a 3.3kV JBS diode.

In this work, we have evaluated 4° off-axis Si face 4H-SiC MOSFETs channel performance along both the [11-20] (perpendicular to steps) and [1-100] (parallel to steps) orientations, to evidence possible anisotropy on Si-face due to roughness scattering effect. Improved gate oxide treatments, allowing low interface state densities and therefore high mobility values, have been used on both NO and N2O annealed gate oxides. With these high channel mobility samples, a small anisotropy effect (up to 10%) can be observed at high electric fields. The anisotropy can be seen both at room and high temperatures. However, the optical phonon scattering is the dominant effect under these biasing conditions.

This work addresses the electrical behaviour of high-voltage (HV) SiC MOSFETs, being the main motivation to check their robustness. Large area (25 mm2) devices rated for 3.3 kV applications were fabricated with a special process for the gate oxide formation. The unit cell was designed to achieve good short-circuit performance. Static and dynamic characterization is presented at room and high temperature. Output curves and 3rdquadrant behaviour were analysed. Dynamic tests were performed at high bus voltages and high current. To check device robustness, short-circuit and power cycling’s were considered. Robustness test results put in evidence the achievement of reasonable good results obtained due to a suitable cell design.

A SiC Schottky dual-diode temperature-sensing element, suitable for both complementary variation of VF with absolute temperature (CTAT) and differential proportional to absolute temperature (PTAT) sensors, is demonstrated over 60–700 K, currently the widest range reported. The structure’s layout places the two identical diodes in close, symmetrical proximity. A stable and high-barrier Schottky contact based on Ni, annealed at 750 °C, is used. XRD analysis evinced the even distribution of Ni2Si over the entire Schottky contact area. Forward measurements in the 60–700 K range indicate nearly identical characteristics for the dual-diodes, with only minor inhomogeneity. Our parallel diode (p-diode) model is used to parameterize experimental curves and evaluate sensing performances over this far-reaching domain. High sensitivity, upwards of 2.32 mV/K, is obtained, with satisfactory linearity (R2 reaching 99.80%) for the CTAT sensor, even down to 60 K. The PTAT differential version boasts increased linearity, up to 99.95%. The lower sensitivity is, in this case, compensated by using a high-performing, low-cost readout circuit, leading to a peak 14.91 mV/K, without influencing linearity.

Edge termination is a critical part of a power devices. Numerous edge termination types have been developed for silicon devices. Implementation of these termination architectures are not straightforward in SiC due to physical and processing specificities: lower junction depths, higher electric field, trench depth and shaping limitations, etc. Two main families of terminations are currently used in commercial devices, pure Field Guard Rings, and JTE + Rings combination. The increasing number of trench commercial devices requires new approaches based on etched rings filled with dielectrics or polysilicon. For epitaxied bipolar devices, MESA with bevel angle termination combined with JTE based architecture are also suitable. In any case, and especially regarding avalanche capability requirements, not only the termination architecture is relevant, but also the passivation type, the channel stopper design, the 3D design. As modelling using conventional tools is not fully reliable, specific complementary characterization methods are needed. For instance, micro-OBIC can be very effective to determine the electric field distribution in the periphery of the power devices.

For over 15 years, the number of studies on graphene electronics has not ceased growing. The rich physics, a set of outstanding properties, and the envisioned range of potential applications have consolidated graphene as a research field in its own. In this Research Update, we address a specific case of graphene for electronics, epitaxial graphene on silicon carbide (SiC) substrates. This paper mainly focuses on the electronic interface of graphene with metals. The first part of this paper describes the most characteristic aspects of the growth of epitaxial graphene on SiC wafers, and the main techniques for graphene material characterization are presented first. The main objective of this paper is to gather and discuss the most representative studies on the graphene–metal interface and the strategies employed to obtain low values for the contact resistances, which is a key feature for achieving the best performance of any graphene electronic devices. To benchmark developments in specifically epitaxial graphene on SiC, we include the results on mechanically exfoliated graphene from HOPG, as well as chemical vapor deposition graphene. In the last part of this paper, relevant device architectures for electrically gating graphene are briefly discussed.

The use of graphene transistors for transducing neural activity has demonstrated the potential to extend the spatiotemporal resolution of electrophysiological methods to lower frequencies, providing a new tool to understand the role of the infra-slow activity.

This paper reviews advanced gate dielectric processes for SiC MOSFETs. The poor quality of the SiO2/SiC interface severely limits the value of the channel field-effect mobility, especially in 4H-SiC MOSFETs. Several strategies have been addressed to overcome this issue. Nitridation methods are effective in increasing the channel mobility and have been adopted by manufacturers for the first generations of commercial power devices. Gate oxide doping techniques have also been successfully implemented to further increase the channel mobility, although device stability is compromised. The use of high-k dielectrics is also analyzed, together with the impact of different crystal orientations on the channel mobility. Finally, the performance of SiC MOSFETs in harsh environments is also reviewed with special emphasis on high temperature operation.

In previous works, an alternative gate oxide configuration, based on a boron treatment, was proposed in order to enhance the SiO2/SiC interface quality, enabling high channel mobility n-channel 4H-SiC lateral MOSFETs. In this paper we study the effect of this treatment on 6H-SiC MOSFETs and we compare it to their 4H-SiC counterparts. The gate oxide boron treatment highly increases mobility values in 4H-SiC whereas the increase is lower in 6H-SiC. The mobility increase by the boron treatment in 4H-SiC MOSFETs is related to the decrease of near interface oxide traps (NIOTs). Then, a different NIOTs density and energy location can be seen as a possible explanation for the different mobility improvement behavior seen in both polytypes.

A new oxide configuration for the development of high mobility 4H-SiC lateral MOSFETs is proposed in this work. The oxide is composed by a rapid thermal oxidation (RTO) in N2O environment, a Boron diffusion into the SiO2 and a PECVD TEOS deposited oxide, in order to improve the interface quality. The obtained MOSFETs show very high peak field effect mobilities ranging from 80 up to more than 170 cm2V-1s-1 in MOSFETs with higher channel length than the tested transistors. The physical (SIMS) and electrical analysis of the oxide and SiC surface reveals that the Boron has not diffused into the SiC. This is most probably due to the high concentration of Nitrogen at the interface generated during the N2O oxidation.

SiC planar VDMOS of three voltages ratings (1.7kV, 3.3kV and 4.5kV) have been fabricated using a Boron diffusion process into the thermal gate oxide for improving the SiO2/SiC interface quality. Experimental results show a remarkable increase of the effective channel mobility which increases the device current capability, especially at room temperatures. At high temperatures, the impact of the Boron treatment is lower since the major contribution of the drift layer to the on-resistance. In addition, the intrinsic body diode characteristics approximate to that of an ideal PiN diode, and the blocking capability is not compromised by the use of Boron for the gate oxide formation.

We performed deep level transient spectroscopy (DLTS), in capacitance, constant-capacitance and current mode, on 5 MeV proton irradiated 4H-SiC p+-i-n diodes. The study has revealed the presence of several majority and minority traps, ranging in the 0.4-1.6 eV below the conduction band edge and in the 0.4-1.5 eV above the valence band edge. We present a comparison of the results obtained with the three modes and discuss the nature of the detected traps, in the light of previous results found in the literature. At last, the impact of the irradiation on the minority carrier lifetime is evaluated by electrical measurements.

This work is the first public presentation regarding a novel, proprietary concept - Delta Reference - for generating sub-1V temperature compensated voltage reference. Delta Reference is capable to sustain a high temperature range and to enable the use of a large variety of temperature sensitive devices. By employing the present concept, we are able to generate thermal compensated voltage reference having the same temperature coefficient (TC) such as the well-known bandgap reference, but with multiple added advantages.

This paper introduces the newest proprietary concept called Delta-Reference voltage generator. It is able to generate sub-1V, high temperature compensated voltage reference implemented on silicon carbide (SiC) devices. Hereby, we experimentally demonstrate the functionality of Delta-Reference concept based on a large variety of temperature-dependent SiC devices. Delta-Reference is comparable to the well-known Bandgap-Reference in terms of temperature coefficient (TC), but our new approach is more versatile and comes with additional benefits, being a right candidate for a new generation of voltage reference addressed to high temperature, power management, and space applications.

This work describes a novel analysis method for the power cycling test, developed for high-voltage and temperature silicon carbide diodes. The silicon carbide devices working at temperatures beyond 170 °C, the maximum temperature rating for silicon devices, need specific reliability tests adapted to high temperature operation of this new generation of power devices. The specificity of the further presented method consist in the use of 10 ms sinusoidal power current pulses that are able to evidence the temperature developed inside the diode during the power pulse, the temperature characteristic delay versus the applied current and the temperature calibration method. Moreover, this overall method is able to evidence the transformations occurred in the bonding contact and the dye attach.

This paper describes an original method for very short minority carrier lifetime evaluation of semiconductor junctions that is aimed to be mainly used for the surface recombination studies of bipolar junction transistors made on silicon carbide, where an important surface recombination between base and emitter occurs. The presented method is based on combined electrooptical measurements and it was prior tested and calibrated using silicon bipolar transistors.

International audience; Thanks to its high throughput and low cost of ownership Plasma Immersion Ion Implantation (or Plasma Doping) has been widely used for Memory device fabrication. Its ability to implant very high doses in shallow layers, makes it a perfect tool for new material modification applications needed for advanced logic devices. Nevertheless, few works are reported for its uses in power device fabrication. The aim of this paper is to present several application cases where we studied the use of our PULSION® PIII tool for implantation in Silicon, Silicon Carbide and Gallium Nitride power devices. Benefits of PIII and challenges to overcome will be discussed for the following applications in silicon devices: High dose phosphorus and boron implantation for polysilicon gate doping and low dose doping of deep trench superjunction applications, contact plug doping for Silicon SFET devices and wall doping of deep shallow trenches for IGBTs. In addition possible applications for wide band gap materials will be discussed with an example of doping application for GaN HEMT, where PIII allowed to make the first demonstration of a normally-off device. Finally some doping and material modification applications on SiC are presented.

In this paper, the result of a long term HTRB Test with a test time over 5000 hours on novel 3.3kV SiC-JBS-Diodes is presented. The diodes under test have an area of 5×5mm2 with a p-stripe design and a JTE-based edge-termination. Two splits were tested, one with globtop cover underneath silicone gel potting and the other with gel potting only. Both splits show a significant decrease in leakage current over the course of the test. A different behavior of leakage current is observed when test conditions are reapplied after an interruption for intermediate measurements. It is evident that the leakage current is not only affected by the chip but also by the surrounding materials. Both splits passed over 5000 hours without failure.

This paper shows the effect of performing consecutive measurement prior to negative bias stress instability (NBSI) on diamond metal–oxide–semiconductor capacitor (MOSCAP). For the first time, time-dependent stress tests have been carried out in order to investigate the stability of the flatband voltage ( ${V}_{\text {FB}}$ ) of MOSCAPs through capacitance–voltage ( CV ) measurements. Two tests have been performed. In the first test, consecutive CV measurements with the device biased from deep depletion to the accumulation regime were performed to monitor the recovery of the ${V}_{\text {FB}}$ . In the second test, NBSI technique has been applied. ${V}_{\text {FB}}$ stability has been measured by means of a time-dependent bias stress in which the device was polarized at a fixed negative voltage for a specific time interval prior to performing the next CV measurement. As ${V}_{\text {FB}}$ is directly connected to the effective oxide charge ( ${N}_{\text {eff}}$ ), the two different tests allowed the extraction of total amount of ${N}_{\text {eff}}$ that interfered during the measurements. The result observed shows that the postoxidation annealing process induces a strong enhancement of the MOSCAP stability together with a decrease of ${N}_{\text {eff}}$

Brain-computer interfaces and neural prostheses based on the detection of electrocorticography (ECoG) signals are rapidly growing fields of research. Several technologies are currently competing to be the first to reach the market; however, none of them fulfill yet all the requirements of the ideal interface with neurons. Thanks to its biocompatibility, low dimensionality, mechanical flexibility, and electronic properties, graphene is one of the most promising material candidates for neural interfacing. After discussing the operation of graphene solution-gated field-effect transistors (SGFET) and characterizing their performance in saline solution, it is reported here that this technology is suitable for μ-ECoG recordings through studies of spontaneous slow-wave activity, sensory-evoked responses on the visual and auditory cortices, and synchronous activity in a rat model of epilepsy. An in-depth comparison of the signal-to-noise ratio of graphene SGFETs with that of platinum black electrodes confirms that graphene SGFET technology is approaching the performance of state-of-the art neural technologies.

Recording infraslow brain signals (, This work was funded by the European Union’s Horizon 2020 research and innovation programme under grant agreement no. 696656 (Graphene Flagship) and no. 732032 (BrainCom). This work has made use of the Spanish ICTS Network MICRONANOFABS partially supported by MINECO and the ICTS ‘NANBIOSIS’, more specifically by the Micro-NanoTechnology Unit of the CIBER in Bioengineering, Biomaterials and Nanomedicine (CIBER-BBN) at the IMB-CNM. E.M.C. acknowledges that this work has been done in the framework of the PhD in Electrical and Telecommunication Engineering at the Universitat Autònoma de Barcelona. E..C. thanks the Spanish Ministerio de Economía y Competitividad for the Juan de la Cierva postdoctoral grant IJCI-2015–25201. T. Durduran acknowledges support from Fundació CELLEX Barcelona, Ministerio de Economía y Competitividad /FEDER (PHOTODEMENTIA, DPI2015–64358-C2–1-R), the “Severo Ochoa” Programme for Centres of Excellence in R&D (SEV-2015–0522) and the Obra Social “la Caixa” Foundation (LlumMedBcn). M.V.S.V. acknowledges support from MINECO BFU2017-85048-R. ICN2 is supported by the Severo Ochoa programme fromSpanish MINECO (grant no. SEV-2017-0706).

In this work, Silicon Carbide Schottky Barrier Diodes (SBDs) were inspected by Infrared Lock-In Thermography to study and determine the origin of structural weak spots resulting from their manufacturing and electro-thermal stressing tests. These spots are frequency modulated following three different approaches representative of the SBDs operating regimes and detected by their infrared emission, as they behave as hot spots. According to thermal results, such weak spots have originated from barrier modification due to the wire-bonding process, non-uniform active area resistance due to bad metallization electrical contact, deep level traps creation due to high energy implantation in the edge termination, and internal propagation of lattice defects during thermal cycling.

Graphene is a 2D material with potential for almost any purpose, thanks to a combination of excellent characteristics, e.g. high electrical conductivity. Graphene grown on SiC wafers is one of the promising routes for graphene integration into planar technology electronic applications. Synthesis is based on the decomposition of a SiC single crystal surface at high temperature, where Si-terminated SiC substrates require the formation of the C buffer layer. In spite of numerous experimental and theoretical works the understanding and control upon crucial factors such as step and terrace stability or surface roughening is far from been fully comprehended and then technologically optimized. We present experimental results on the deposition of graphene onto Si-terminated 6H-SiC. We analyze the effect of ex situ and in situ conditionings of the SiC surface in the thermal decomposition and reconstruction of the SiC terraces, toward higher control upon the growth process of graphene films.

This paper is an important step toward the development of complex integrated circuit (IC) control electronics that have to attend to high-temperature environment power applications. We present in premiere a prototype set of essential mixed-signal ICs on SiC capable of controlling power switches and a lateral power MESFET able to operate at high temperatures, all embedded on the same chip. Also, we report for the first time the functionality of standard Si-CMOS topologies on SiC for the master–slave data flip-flop (FF) and data-reset FF digital building blocks designed with MESFETs. Concretely, we present the complete development of SiC-MESFET IC circuitry, able to integrate gate drivers for SiC power devices. This development is based on the mature and stable Tungsten–Schottky interface technology used for the fabrication of stable SiC Schottky diodes for the European Space Agency Mission BepiColombo.

This work describes experimental surge current evaluation for various layout design of 1.2kV 4H-SiC JBS diodes. The silicon carbide devices working at temperatures significantly beyond to those of silicon power devices need specific reliability tests, adapted to high temperature operation and/or high power density of this new generation of power devices. Actually, it is not possible to predict the surge current capability by computer simulation because of 3-D effects that occur at high current density. Therefore the only available method for surge current characterization is the experiment. The use of 10ms sinusoidal power current pulses is able to evidence by the I-V characteristic, the temperature developed inside the diode during the power pulse, and the bipolar activation characteristic during the applied power.

Recent advances and new trends in high voltage SiC based MOSFETs are analyzed. The main focus is done on design optimization strategies for reducing the on-state resistance. Gate oxide treatments for improving the interface quality resulting in a lower channel resistance are reviewed as well as solutions for lowering the JFET and bulk resistance components. The 3rd quadrant operation, short-circuit capability and switching performance are analyzed together with design strategies for their improvement. Finally, the limits of high voltage MOSFETs are outlined and future power devices to overcome the MOSFETs limits in ultra-high voltage applications are presented.

Silicon photodiodes are very useful devices as X-ray beam monitors in synchrotron radiation beamlines, as well as other astronomy and space applications. Owing to their lower susceptibility to variable temperature and illumination conditions, there is also special interest in silicon carbide devices for some of these applications. Moreover, radiation hardness of the involved technologies is a major concern for high-energy physics and space applications. This work presents four-quadrant photodiodes produced on ultrathin (10 μm) and bulk Si, as well as on SiC epilayer substrates. An extensive electrical characterization has been carried out by using current-voltage (I-V) and capacitance-voltage (C-V) techniques. The impact of different temperature (from -50C to 175C) and visible light conditions on the electrical characteristics of the devices has been evaluated. Radiation effects caused by 2 MeV electron irradiation up to 1×1014, 1×1015 and 1×1016 e/cm2 fluences have been studied. Special attention has been devoted to the study of charge build-up in diode interquadrant isolation, as well as its impact on interquadrant resistance. The study of these electrical properties and its radiation-induced degradation should be taken into account for device applications.

This paper presents an experimental investigation of the dynamic performance of SiC 6.5kV JBS diodes. Using a hybrid Si SPT IGBT/SiC JBS diodes combination, we have analyzed the turn-off behavior limits of SiC JBS diodes and compared the result against a state-of-the-art Si PiN diode. The experimental results show that the JBS diodes can handle about 40A/chip at 125°C before going into thermal runaway. This maximum turn-off current value increases by about 50% when the diodes are operated at room temperature. The diodes dI/dt behaviour appear to be virtually independent of the DC-link voltage (at R G =18Ω). The comparison between turn-off curves for 6.5kV SiC and Si diodes shows that the use of SiC JBS diodes reduces the reverse recovery losses by more than 98%.

A new gate oxide configuration, including a Boron treatment, is reported in this work. It is designed to improve the SiO 2 /SiC interface quality in 4H-SiC N-MOSFETs. The obtained results show high field effect mobilities up to 160 cm2/Vs. The fabricated devices have also been undergone to a BSI stress up to 20 h at room temperature showing good threshold voltage stability. The physical (SIMS) analysis of the oxide and SiC surface reveals that Boron has not diffused into the SiC.

A new process technology for 4H-SiC planar power MOSFETs based on a Boron diffusion step to improve the SiO2/SiC interface quality is presented in this work. Large area (up to 25 mm2) power MOSFETs of three voltages ratings (1.7 kV, 3.3 kV and 4.5 kV) have been fabricated showing significant improvements in terms of inversion channel mobility and on-resistance in comparison with counterparts without Boron oxide treatment. Experimental results show a remarkable increase of the channel mobility, which raises the device current capability, especially at room temperature. When operating at high temperature, the impact of the high channel mobility due to Boron treatment on electrical forward characteristics is reduced as the drift layer resistance starts to dominate in the total on-state resistance. In addition, the 3rd quadrant characteristics approximate to those of an ideal PiN diode, and the device blocking capability is not compromised by the use of Boron for the gate oxide formation. The experimental performance in a simple DC/DC converter is also presented., This work has been partially supported by the EU through the SPEED FP7 Large Project (NMP3-LA-2013-604057) and by the research program from the Spanish Ministry of “Economía y Competitividad” HiVolt-Tech (TEC2014-54357-C2-1-R) cofunded by the EU-ERDF (FEDER)

This work presents the 10 MeV protons irradiation effects on 4H-SiC MOSFETs at different fluences. MOSFETs main electrical parameters, such as the channel mobility (µEFF), threshold voltage (VTH), transconductance (gm) and subthreshold current, were analyzed using the time bias stress instability (BSI) technique. Applying this method allowed us to study the effect of carriers interaction with generated interface traps, whether in the bulk or at the interface. Improvements, such as VTHstabilization in time and a significant increase of the µEFFat high fluencies, have been noticed. We assume that this behavior is connected with the atomic diffusion from the SiO2/SiC interface, towards the epilayer during proton irradiation. These atoms, in majority Nitrogen, may create other bonds by occupying various vacancies coming from Silicon and Carbon’s dangling bond. Therefore, by enhancing the passivated Carbon atoms number, we show that high irradiation proton could be a way to improve the SiO2/SiC interface quality.