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The thermal stability of joints in thermoelectric (TE) modules, which are degraded during interdiffusion between the TE material and the contacting metal, needs to be addressed in order to utilize TE technology for competitive, sustainable energy applications. Herein, we deposit a 200 nm-thick Zr-based thin-film metallic glass (TFMG), which acts as an effective diffusion barrier layer with low electrical contact resistivity, on a high-zT Se-doped AgSbTe2 substrate. The reaction couples structured with TFMG/TE are annealed at 673 K for 8–360 hours and analyzed by electron microscopy. No observable IMCs (intermetallic compounds) are formed at the TFMG/TE interface, suggesting the effective inhibition of atomic diffusion that may be attributed to the grain-boundary-free structure of TFMG. The minor amount of Se acts as a tracer species, and a homogeneous Se-rich region is found nearing the TFMG/TE interface, which guarantees satisfactory bonding at the joint. The diffusion of Se, which has the smallest atomic volume of all the elements from the TE substrate, is found to follow Fick’s second law. The calculated diffusivity (D) of Se in TFMG falls in the range of D~10−20–10−23(m2/s), which is 106~107 and 1012~1013 times smaller than those of Ni [10−14–10−17(m2/s)] and Cu [10−8–10−11(m2/s)] in Bi2Te3, respectively.

The thin film metallic glass (TFMG) is an effective diffusion barrier layer for PbTe-based thermoelectric (TE) modules. Reaction couples structured with Cu/TFMG/PbTe are prepared via sputter-deposition and are annealed at 673 K for 8-96 h. The transmission line method is adopted for the assessment of electrical contact resistivity upon the PbTe/TFMG, and the value remains in the range of 3.3-2.5 × 10−9 (Ω m2). The titanium-based TFMG remains amorphous upon annealing at 673 K for 48 h and effectively blocks the inter-diffusion by not having grain-boundaries, which only allows the bulk diffusion between the metal electrode and the TE substrate.

The thermal stability of joints in thermoelectric (TE) modules, which are degraded during interdiffusion between the TE material and the contacting metal, needs to be addressed in order to utilize TE technology for competitive, sustainable energy applications. Herein, we deposit a 200 nm-thick Zr-based thin-film metallic glass (TFMG), which acts as an effective diffusion barrier layer with low electrical contact resistivity, on a high-zT Se-doped AgSbTe2 substrate. The reaction couples structured with TFMG/TE are annealed at 673 K for 8–360 hours and analyzed by electron microscopy. No observable IMCs (intermetallic compounds) are formed at the TFMG/TE interface, suggesting the effective inhibition of atomic diffusion that may be attributed to the grain-boundary-free structure of TFMG. The minor amount of Se acts as a tracer species, and a homogeneous Se-rich region is found nearing the TFMG/TE interface, which guarantees satisfactory bonding at the joint. The diffusion of Se, which has the smallest atomic volume of all the elements from the TE substrate, is found to follow Fick’s second law. The calculated diffusivity (D) of Se in TFMG falls in the range of D~10−20–10−23(m2/s), which is 106~107 and 1012~1013 times smaller than those of Ni [10−14–10−17(m2/s)] and Cu [10−8–10−11(m2/s)] in Bi2Te3, respectively.

A phase-locked loop (PLL)-based frequency synthesizer at 5 GHz is designed and fabricated in 0.18-mum CMOS technology. The power consumption of the synthesizer is significantly reduced by using an injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. The synthesizer chip consumes 18 mW of power, of which only 3.93 mW is consumed by the voltage-controlled oscillator (VCO) and the ILFD at 1.8-V supply voltage. The VCO has the phase noise of - 104 dBc/Hz at 1-MHz offset and an output tuning range of 740 MHz. The chip size is 1.1 mm times 0.95 mm.

A K-band low-noise amplifier (LNA) is designed and fabricated in a standard 0.18 μm CMOS technology. A design method of CMOS LNA is used to render the optimum source resistance (R opt ) close to 50 Ω and Z in =Z opt ∗ by using small devices and small bias currents. This LNA chip achieves a peak gain of 13.5 dB and a noise figure of 4.7 dB at 24 GHz. The supply voltage and current are 1 V and 8.3 mA, respectively. The input and output return losses are lower than −10 dB, the input referred 1-dB compression P 1db is −7 dBm, and the chip size is 0.64 mm × 0.48 mm.