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The switched-capacitor converter (SCC) has been widely used for voltage regulation in multicore chips, where energy efficiency is the major concern. However as the overhead to integrate SCCs in a chip is non-negligible, the SCCs could not be overused. Hence in this paper we propose an early stage SCCs planning framework to obtain the SCC supply scheme together with the optimized Metal-Insulator-Metal (MIM) capacitance allocation and converter ratio selection for each SCC when the given number of SCCs is less than the number of cores. Besides, our method could also explore to find the best number of used SCCs for a given chip. The experiments show the results of our SCC planning methods.

The convolutional and deep neural networks are prevalent machine learning algorithms for real-world applications. As the neural network needs large computations, many artificial intelligence (AI) chips are designed to accelerate the computation. AI chips have achieved better energy efficiency and high computational capacity in the neural network implementation. The communication network in AI chips influences the data transformation and hardware efficiency. The network-on-chip (NoC) is one feasible solution to meet the data communication requirements in AI chips. This paper introduces the communication network in AI chips and the strategy of mapping neural network to chips with the extensible hierarchical architecture. We also conclude the opportunities for communication optimization in the design of AI chips. In this paper, we propose our processor architecture and optimize the performance and energy of intracommunication in chips from three aspects: data reuse, topology, and router architecture. The experimental results show that our optimization can totally achieve 25.31× latency reduction and 79.92× energy less than the baseline. The results show that our design can reduce the latency by 5.47× and save communication energy by 7.5× when compared with the state-of-the-art design DaDianNao. When compared with another design Eyeriss, our design can reduce latency by 7.57× and save communication energy by 3.03×.