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In recent years, the SiC power semiconductor has emerged as an attractive alternative that pushes the limitations of junction temperature, power rating, and switching frequency of Si devices. These advanced properties will lead converters to higher power density. However, the reliability of the SiC semiconductor is still under investigation, and at the same time, the standard Si device packages do not meet the requirement of high temperature operation. In order to take full advantage of SiC semiconductor devices, high density, high temperature device packaging needs to be developed. In this dissertation, a high temperature wirebond package for multi-chip phase-leg power module using SiC devices was designed, developed, fabricated and tested. The details of the material selection and thermo-mechanical reliability evaluation are described. High temperature power test shows that the presented package can perform well at the high junction temperature. In order to increase the power density, reduce the parasitic parameters, and enhance the electrical, thermo-mechanical performance over wirebond packages, planar package is utilized to better take advantages of SiC device. This dissertation proposed a novel package, in which the interconnections can be formed on small dimensional pads and enclosed pads that may baffle the regular solder based connection in other planar packages. Electrical and thermo-mechanical tests of the prototype module demonstrate the functionality and reliability of the presented planar packaging methodology. In this dissertation, together with the design example, the manual module layout design and automatic module layout design process are also presented. Furthermore, a systematic optimal design process and parametric study of the heatsink-fan cooling system by applying the analytical model is described. This dissertation also established a systematic testing procedure which can rapidly detect defects and reduce the risk in high temperature packaging testing. Finally, a wirebond module and a planar module are designed for 175 ºC junction temperature and 250 ºC junction temperatures. All the key concepts and ideas developed in this work are implemented in the prototype module development and then verified by the experimental results. Ph. D.

The high-voltage SiC power semiconductor devices have been developed in recent years. They cause an urgent in the need for the power semiconductor packaging to have not only low interconnect resistance, less noise, less parasitic oscillations, improved reliability, and better thermal management, but also High-Voltage (HV) blocking capability. The existing power semiconductor packaging technologies includes wire-bonding interconnect, press pack, flip-chip technology, metal posts interconnected parallel plates structure (MIPPS), dimple array interconnection (DAI), power overlay (POL) technology, and embedded power (EP) technology. None of them meets the requirements of low profile and high voltage rating. The objective of the work in this dissertation is to propose and design a high-voltage power semiconductor device packaging method with low electric field stress and low profile to meet the requirments of high-voltage blocking capability. The main contributions of the work presented in this dissertation are: 1. Understanding the electric field distribution in the package. The power semiconductor packaging is simulated by using Finite Element Analysis (FEA) software. The electric field distribution is known and the locations of high electric field concentration are identified. 2. Development of planar high-voltage power semiconductor device packaging method With the proposed structure in the dissertation, the electric field distribution of a planar device package is improved and the high electric field intensity is relieved. 3. Development of design guidelines for the propsed planar high-voltage device packaging method. The influence of the structure dimensions and the material properties is studied. An optimal design is identified. The design guideline is given. 4. Fabrication and experimental verification of the proposed high-voltage device packaging method A detailed fabrication procedure which follows the design guideline is presented. The fabricated modules are tested by using a high power curve tracer. Test results verify the proposed method. 5. Simplification of the structure model of the proposed device package The package structure model is simplified through the elimination of power semiconductor device internal structure model. The simplified model can be simulated by a non-power device simulator. The simulation results of the simplified model match the simulation results of the complete model very well. Ph. D.