99 results on '"Poiroux, Thierry"'
Search Results
2. Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements
3. Physical and Technological Limitations of NanoCMOS Devices to the End of the Roadmap and Beyond
4. Advanced CMOS Devices on Bulk and SOI: Physics, Modeling and Characterization
5. Multiple Gate Technologies
6. Compact Modeling of Double Gate MOSFET for IC Design
7. Influence of device architecture on junction leakage in low-temperature process FDSOI MOSFETs
8. Modeling of Doping Effects in Surface Potential Based Compact Model of Fully Depleted SOI MOSFET
9. Back gate impact on the noise performances of 22FDX fully-depleted SOI CMOS
10. L-UTSOI: Best in-class compact modeling solution for FD-SOI technologies
11. Full quantum treatment of remote Coulomb scattering in silicon nanowire FETs
12. Experimental investigation on the quasi-ballistic transport: part II-backscattering coefficient extraction and link with the mobility
13. Experimental investigation on the quasi-ballistic transport: part I-determination of a new backscattering coefficient extraction methodology
14. Size dependence of surface-roughness-limited mobility in silicon-nanowire FETs
15. Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance
16. MOS-like approach for compact modeling of High-Electron-Mobility Transistor
17. L-UTSOI: A compact model for low-power analog and digital applications in FDSOI technology
18. An explicit analytical charge-based model of undoped independent double gate MOSFET
19. Evidence of 2D intersubband scattering in thin film fully depleted silicon-on-insulator transistors operating at 4.2 K
20. In-wafer variability in FD-SOI MOSFETs: detailed analysis and statistical modelling
21. Single Event Transient Compact Model for FDSOI MOSFETs Taking Bipolar Amplification and Circuit Level Arbitrary Generation Into Account
22. Characterization Methodology and Physical Compact Modeling of in-Wafer Global and Local Variability
23. New physical insight for analog application in PSP bulk compact model
24. Compact Modelling of Single Event Transient in Bulk MOSFET for SPICE: Application to Elementary Circuit
25. Experimental ${g}_{m}/{I}_{{D}}$ Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET
26. Sensitivity analysis of C-V global variability for 28 nm FD-SOI
27. Systematic evaluation of the split C-V based parameter extraction methodologies for 28 nm FD-SOI
28. Device level modeling challenges for circuit design methodology in presence of variability
29. Analog and RF modeling of FDSOI UTBB MOSFET using Leti-UTSOI model
30. Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part II: DC and AC Model Description
31. Experimental gm/{I}{D} Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET.
32. REALISATION DUN COMPOSANT ELECTROMECANIQUE POUR UN MICRO- OU NANO- SYSTEME DOTE DUN BARREAU FORMANT UN AXE DE ROTATION DU COMPOSANT ET RECOUVERT DE GRAPHENE
33. Advanced CMOS Devices on Bulk and SOI: Physics, Modeling and Characterization
34. Compact Modeling of Double Gate MOSFET for IC Design
35. Physical and Technological Limitations of NanoCMOS Devices to the End of the Roadmap and Beyond
36. Multiple Gate Technologies
37. Low-Frequency Noise Sources in Advanced UTBB FD-SOI MOSFETs
38. On the Optimization of Ebeam Lithography Using Hydrogen Silsesquioxane (HSQ) for Innovative Self-Aligned CMOS Process
39. Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width
40. Effectiveness of strained-Si technology for thin-body MOSFETs
41. Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) Fully Depleted SOI MOSFETs
42. Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs
43. Surface potential based model of ultra-thin fully depleted SOI MOSFET for IC simulations
44. A wigner function-based determinist method for the simulation of quantum transport in silicon nanowire transistors
45. Multi-$V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit
46. On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells
47. Simulation, modelling and characterisation of quasi-ballistic transport in nanometer sized field effect transistors: from TCAD to atomistic simulation
48. Investigation of bias-dependent series resistances and barrier height in Double Gate Schottky MOSFETs
49. Experimental Comparison Between Sub-0.1-$\mu{\hbox{m}}$ Ultrathin SOI Single- and Double-Gate MOSFETs: Performance and Mobility
50. Device Physics and Modeling
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.