Search

Your search keyword '"Porrmann, Florian"' showing total 10 results
Start Over Author "Porrmann, Florian"
10 results on '"Porrmann, Florian"'

1. VEDLIoT -- Next generation accelerated AIoT systems and applications

Author

Mika, Kevin, Griessl, René, Kucza, Nils, Porrmann, Florian, Kaiser, Martin, Tigges, Lennart, Hagemeyer, Jens, Trancoso, Pedro, Azhar, Muhammad Waqar, Qararyah, Fareed, Zouzoula, Stavroula, Ménétrey, Jämes, Pasin, Marcelo, Felber, Pascal, Marcus, Carina, Brunnegard, Oliver, Eriksson, Olof, Salomonsson, Hans, Ödman, Daniel, Ask, Andreas, Casimiro, Antonio, Bessani, Alysson, Carvalho, Tiago, Gugala, Karol, Zierhoffer, Piotr, Latosinski, Grzegorz, Tassemeier, Marco, Porrmann, Mario, Heyn, Hans-Martin, Knauss, Eric, Mao, Yufei, and Meierhöfer, Franz

Subjects
Computer Science - Hardware Architecture, Computer Science - Artificial Intelligence, Computer Science - Cryptography and Security
Abstract

The VEDLIoT project aims to develop energy-efficient Deep Learning methodologies for distributed Artificial Intelligence of Things (AIoT) applications. During our project, we propose a holistic approach that focuses on optimizing algorithms while addressing safety and security challenges inherent to AIoT systems. The foundation of this approach lies in a modular and scalable cognitive IoT hardware platform, which leverages microserver technology to enable users to configure the hardware to meet the requirements of a diverse array of applications. Heterogeneous computing is used to boost performance and energy efficiency. In addition, the full spectrum of hardware accelerators is integrated, providing specialized ASICs as well as FPGAs for reconfigurable computing. The project's contributions span across trusted computing, remote attestation, and secure execution environments, with the ultimate goal of facilitating the design and deployment of robust and efficient AIoT systems. The overall architecture is validated on use-cases ranging from Smart Home to Automotive and Industrial IoT appliances. Ten additional use cases are integrated via an open call, broadening the range of application areas., Comment: This publication incorporates results from the VEDLIoT project, which received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 957197. CF'23: 20th ACM International Conference on Computing Frontiers, May 2023, Bologna, Italy

Published
2023
Full Text
View/download PDF

2. VEDLIoT: Very Efficient Deep Learning in IoT

Author

Kaiser, Martin, Griessl, Rene, Kucza, Nils, Haumann, Carola, Tigges, Lennart, Mika, Kevin, Hagemeyer, Jens, Porrmann, Florian, Rückert, Ulrich, dem Berge, Micha vor, Krupop, Stefan., Porrmann, Mario, Tassemeier, Marco, Trancoso, Pedro, Quararyah, Fareed, Zouzoula, Stavroula, Casimiro, Antonio, Bessani, Alysson, Cecilio, Jose, Andersson, Stefan, Brunnegard, Oliver, Eriksson, Olof, Weiss, Roland, Meierhöfer, Franz, Salomonsson, Hans, Malekzadeh, Elaheh, Ödman, Daniel, Khurshid, Anum, Felber, Pascal, Pasin, Marcelo, Schiavoni, Valerio, Ménétrey, Jämes, Gugula, Karol, Zierhoffer, Piotr, Knauss, Eric, and Heyn, Hans-Martin

Subjects
Computer Science - Hardware Architecture, Computer Science - Cryptography and Security, Computer Science - Distributed, Parallel, and Cluster Computing, Computer Science - Performance
Abstract

The VEDLIoT project targets the development of energy-efficient Deep Learning for distributed AIoT applications. A holistic approach is used to optimize algorithms while also dealing with safety and security challenges. The approach is based on a modular and scalable cognitive IoT hardware platform. Using modular microserver technology enables the user to configure the hardware to satisfy a wide range of applications. VEDLIoT offers a complete design flow for Next-Generation IoT devices required for collaboratively solving complex Deep Learning applications across distributed systems. The methods are tested on various use-cases ranging from Smart Home to Automotive and Industrial IoT appliances. VEDLIoT is an H2020 EU project which started in November 2020. It is currently in an intermediate stage with the first results available., Comment: This publication incorporates results from the VEDLIoT project, which received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 957197

Published
2022
Full Text
View/download PDF

3. VEDLIoT

Author

Mika, Kevin, primary, Griessl, René, additional, Kucza, Nils, additional, Porrmann, Florian, additional, Kaiser, Martin, additional, Tigges, Lennart, additional, Hagemeyer, Jens, additional, Trancoso, Pedro, additional, Azhar, Muhammad Waqar, additional, Qararyah, Fareed, additional, Zouzoula, Stavroula, additional, Ménétrey, Jämes, additional, Pasin, Marcelo, additional, Felber, Pascal, additional, Marcus, Carina, additional, Brunnegard, Oliver, additional, Eriksson, Olof, additional, Salomonsson, Hans, additional, Ödman, Daniel, additional, Ask, Andreas, additional, Casimiro, Antonio, additional, Bessani, Alysson, additional, Carvalho, Tiago, additional, Gugala, Karol, additional, Zierhoffer, Piotr, additional, Latosinski, Grzegorz, additional, Tassemeier, Marco, additional, Porrmann, Mario, additional, Heyn, Hans-Martin, additional, Knauss, Eric, additional, Mao, Yufei, additional, and Meierhöfer, Franz, additional

Published
2023
Full Text
View/download PDF

4. Evaluation of heterogeneous AIoT Accelerators within VEDLIoT

Author

Griessl, René, Porrmann, Florian, Kucza, Nils, Mika, Kevin, Hagemeyer, Jens, Kaiser, Martin, Porrmann, M., Tassemeier, M., Flottmann, M., Qararyah, F., Waqar, M., Trancoso, P., Ödman, D., Gugala, K., and Latosinski, G.

Abstract

Within VEDLIoT, a project targeting the development of energy-efficient Deep Learning for distributed AIoT applications, several accelerator platforms based on technologies like CPUs, embedded GPUs, FPGAs, or specialized ASICs are evaluated. The VEDLIoT approach is based on modular and scalable cognitive IoT hardware platforms. Modular microserver technology enables the integration of different, heterogeneous accelerators into one platform. Benchmarking of the different accelerators takes into account performance, energy efficiency and accuracy. The results in this paper provide a solid overview regarding available accelerator solutions and provide guidance for hardware selection for AIoT applications from far edge to cloud. VEDLIoT is an H2020 EU project which started in November 2020. It is currently in an intermediate stage. The focus is on the considerations of the performance and energy efficiency of hardware accelerators. Apart from the hardware and accelerator focus presented in this paper, the project also covers toolchain, security and safety aspects. The resulting technology is tested on a wide range of AIoT applications.

Published
2023

6. Accelerating binary string comparisons with a scalable, streaming-based system architecture based on FPGAs

Author

Pilz, Sarah, Porrmann, Florian, Kaiser, Martin, Hagemeyer, Jens, Hogan, James M., Rückert, Ulrich, Pilz, Sarah, Porrmann, Florian, Kaiser, Martin, Hagemeyer, Jens, Hogan, James M., and Rückert, Ulrich

Abstract

This paper is concerned with Field Programmable Gate Arrays (FPGA)-based systems for energy-efficient high-throughput string comparison. Modern applications which involve comparisons across large data sets-such as large sequence sets in molecular biology-are by their nature computationally intensive. In this work, we present a scalable FPGA-based system architecture to accelerate the comparison of binary strings. The current architecture supports arbitrary lengths in the range 16 to 2048-bit, covering a wide range of possible applications. In our example application, we consider DNA sequences embedded in a binary vector space through Locality Sensitive Hashing (LSH) one of several possible encodings that enable us to avoid more costly character-based operations. Here the resulting encoding is a 512-bit binary signature with comparisons based on the Hamming distance. In this approach, most of the load arises from the calculation of the O(m * n) Hamming distances between the signatures, where m is the number of queries and n is the number of signatures contained in the database. Signature generation only needs to be performed once, and we do not consider it further, focusing instead on accelerating the signature comparisons. The proposed FPGA-based architecture is optimized for high-throughput using hundreds of computing elements, arranged in a systolic array. These core computing elements can be adapted to support other string comparison algorithms with little effort, while the other infrastructure stays the same. On a Xilinx Virtex UltraScale+ FPGA (XCVU9P-2), a peak throughput of 75.4 billion comparisons per second-of 512-bit signatures-was achieved, using a design with 384 parallel processing elements and a clock frequency of 200 MHz. This makes our FPGA design 86 times faster than a highly optimized CPU implementation. Compared to a GPU design, executed on an NVIDIA GTX1060, it performs nearly five times faster.

Published
2020

10. Acceleration of the SPADE Method Using a Custom-Tailored FP-Growth Implementation

Author

Porrmann, Florian, Pilz, Sarah, Stella, Alessandra, Kleinjohann, Alexander, Denker, Michael, Hagemeyer, Jens, and Rückert, Ulrich

Subjects
low power, embedded devices, Biomedical Engineering, Neuroscience (miscellaneous), parallel and distributed computing, performance optimization, heterogeneous computing, Computer Science Applications, Technology and Code, ddc:610, spike train analysis, Neuroscience, FP-growth, pattern mining
Abstract

Frontiers in neuroinformatics 15, 723406 (2021). doi:10.3389/fninf.2021.723406, Published by Frontiers Research Foundation, Lausanne

Full Text
View/download PDF

Catalog

Books, media, physical & digital resources
See catalog results