Search

none 12 si In this paper we present D.A.V.I.D.E. (Development for an Added Value Infrastructure Designed in Europe), an innovative and energy efficient High Performance Computing cluster designed by E4 Computer Engineering for PRACE (Partnership for Advanced Computing in Europe). D.A.V.I.D.E. is built using best-in-class components (IBM’s POWER8-NVLink CPUs, NVIDIA TESLA P100 GPUs, Mellanox InfiniBand EDR 100 Gb/s networking) plus custom hardware and an innovative system middleware software. D.A.V.I.D.E. features (i) a dedicated power monitor interface, built around the BeagleBone Black Board that allows high frequency sampling directly from the power backplane and scalable integration with the internal node telemetry and system level power management software; (ii) a custom-built chassis, based on OpenRack form factor, and liquid cooling that allows the system to be used in modern, energy efficient, datacenter; (iii) software components designed for enabling fine grain power monitoring, power management (i.e. power capping and energy aware job scheduling) and application power profiling, based on dedicated machine learning components. Software APIs are offered to developers and users to tune the computing node performance and power consumption around on the application requirements. The first pilot system that we will deploy at the beginning of 2017, will demonstrate key HPC applications from different fields ported and optimized for this innovative platform. open Abu Ahmad, Wissam; Bartolini, Andrea; Beneventi, Francesco; Benini, Luca; Borghesi, Andrea; Cicala, Marco; Forestieri, Privato; Gianfreda, Cosimo; Gregori, Daniele; Libri, Antonio; Spiga, Filippo; Tinti, Simone Abu Ahmad, Wissam; Bartolini, Andrea; Beneventi, Francesco; Benini, Luca; Borghesi, Andrea; Cicala, Marco; Forestieri, Privato; Gianfreda, Cosimo; Gregori, Daniele; Libri, Antonio; Spiga, Filippo; Tinti, Simone

The Community Atmosphere Model (CAM) has been ported, redesigned, and scaled to the full system of the Sunway TaihuLight, and provides peta-scale climate modeling performance. Based on a novel domain decomposition method, we have fully optimized the complete model code by using both OpenACC refactoring and more aggressive and finer-grained Athread approaches. The Athread approach enables us to achieve exceptional memory control and usage, efficient vectorization, and sophisticated utilization of the thread-level communication mechanism. We have also further refined the load-balance behaviors towards ultra-large-scale numerical simulation. By combining all these novelties, we achieved a simulation speed of 7.2 and 25.6 simulation-year-per-day (SYPD) for global 25-km and 100-km resolution, respectively (1.2- to 2.2-fold improvements over previous efforts), and a sustainable double-precision performance of 3.3 PFlops for a 750 m global simulation when using 10,075,000 cores.

Nowadays, GPU accelerators are commonly used to speed up general-purpose computing tasks on a variety of hardware. However, due to the diversity of GPU architectures and processed data, optimization of codes for a particular type of hardware and specific data characteristics can be extremely challenging. The autotuning of performance-relevant source-code parameters allows for automatic optimization of applications and keeps their performance portable. Although the autotuning process typically results in code speed-up, searching the tuning space can bring unacceptable overhead if (i) the tuning space is vast and full of poorly-performing implementations, or (ii) the autotuning process has to be repeated frequently because of changes in processed data or migration to different hardware. In this paper, we introduce a novel method for searching generic tuning spaces. The tuning spaces can contain tuning parameters changing any user-defined property of the source code. The method takes advantage of collecting hardware performance counters (also known as profiling counters) during empirical tuning. Those counters are used to navigate the searching process towards faster implementations. The method requires the tuning space to be sampled on any GPU. It builds a problem-specific model, which can be used during autotuning on various, even previously unseen inputs or GPUs. Using a set of five benchmarks, we experimentally demonstrate that our method can speed up autotuning when an application needs to be ported to different hardware or when it needs to process data with different characteristics. We also compared our method to state of the art and show that our method is superior in terms of the number of searching steps and typically outperforms other searches in terms of convergence time.

The Internet of Things (IoT) is a network of physical, connected devices providing services through private networks and the Internet. The devices connect through the Internet to Web servers and other devices. One of the popular programming languages for communicating Web pages and Web apps is JavaScript (JS). Hence, the devices would benefit from JS apps. However, porting JS apps to the many IoT devices, e.g., System-on-a-Chip (SoCs) devices (e.g., Arduino Uno), is challenging because of their limited memory, storage, and CPU capabilities. Also, some devices may lack hardware/software capabilities for running JS apps "as is". Thus, we propose MoMIT, a multiobjective optimization approach to miniaturize JS apps to run on IoT devices. We implement MoMIT using three different search algorithms. We miniaturize a JS interpreter and measure the characteristics of 23 apps before/after applying MoMIT. We find reductions of code size, memory usage, and CPU time of 31%, 56%, and 36%, respectively (medians). We show that MoMIT allows apps to run on up to two additional devices in comparison to the original JS interpreter.

Rust is a relatively new programming language that targets efficient and safe systems-level applications. It includes a sophisticated type system that allows for provable memory- and thread-safety, and is explicitly designed to take the place of unsafe languages such as C and C++ in the coding ecosystem. There is a large existing C and C++ codebase (many of which have been affected by bugs and security vulnerabilities due to unsafety) that would benefit from being rewritten in Rust to remove an entire class of potential bugs. However, porting these applications to Rust manually is a daunting task. In this paper we investigate the problem of automatically translating C programs into safer Rust programs--that is, Rust programs that improve on the safety guarantees of the original C programs. We conduct an in-depth study into the underlying causes of unsafety in translated programs and the relative impact of fixing each cause. We also describe a novel technique for automatically removing a particular cause of unsafety and evaluate its effectiveness and impact. This paper presents the first empirical study of unsafety in translated Rust programs (as opposed to programs originally written in Rust) and also the first technique for automatically removing causes of unsafety in translated Rust programs.

In this work, we demonstrate the process for porting the cloud resolving model (CRM) used in the Energy Exascale Earth System Model Multi-Scale Modeling Framework (E3SM-MMF) from its original Fortran code base to C++ code using a portability library. This porting process is performed using the Yet Another Kernel Library (YAKL), a simplified C++ portability library that specializes in Fortran porting. In particular, we detail our step-by-step approach for porting the System for Atmospheric Modeling (SAM), the CRM used in E3SM-MMF, using a hybrid Fortran/C++ framework that allows for systematic reproduction and correctness testing of gradually ported YAKL C++ code. Additionally, analysis is done on the performance of the ported code using OLCF’s Summit supercomputer.

Subverting the flow of instructions (e.g., by use of code-reuse attacks) still poses a serious threat to the security of today’s systems. Various control flow integrity (CFI) schemes have been proposed as a powerful technique to detect and mitigate such attacks. In recent years, many hardware-assisted implementations of CFI enforcement based on control flow graphs (CFGs) have been presented by academia. Such approaches check whether control flow transfers follow the intended CFG by limiting the valid target addresses. However, these papers all target different platforms and were evaluated with different sets of benchmark applications, which makes quantitative comparisons hardly possible. For this paper, we have implemented multiple promising CFG-based CFI schemes on a common platform comprising a RISC-V within FPGA. By porting almost 40 benchmark applications to this system we can present a meaningful comparison of the various techniques in terms of run-time performance, hardware utilization, and binary size. In addition, we present an enhanced CFI approach that is inspired by what we consider the best concepts and ideas of previously proposed mechanisms. We have made this approach more practical and feature-complete by tackling some problems largely ignored previously. We show with this fine-grained scheme that CFI can be achieved with even less overheads than previously demonstrated.

Spiking neural networks (SNN) are among the most computationally intensive types of simulation models, with node counts on the order of up to 10 11 . Currently, there is intensive research into hardware platforms suitable to support large-scale SNN simulations, whereas several of the most widely used simulators still rely purely on the execution on CPUs. Enabling the execution of these established simulators on heterogeneous hardware allows new studies to exploit the many-core hardware prevalent in modern supercomputing environments, while still being able to reproduce and compare with results from a vast body of existing literature. In this article, we propose a transition approach for CPU-based SNN simulators to enable the execution on heterogeneous hardware (e.g., CPUs, GPUs, and FPGAs), with only limited modifications to an existing simulator code base and without changes to model code. Our approach relies on manual porting of a small number of core simulator functionalities as found in common SNN simulators, whereas the unmodified model code is analyzed and transformed automatically. We apply our approach to the well-known simulator NEST and make a version executable on heterogeneous hardware available to the community. Our measurements show that at full utilization, a single GPU achieves the performance of about 9 CPU cores. A CPU-GPU co-execution with load balancing is also demonstrated, which shows better performance compared to CPU-only or GPU-only execution. Finally, an analytical performance model is proposed to heuristically determine the optimal parameters to execute the heterogeneous NEST.

Classical molecular dynamics (MD) calculations represent a significant part of the utilization time of high-performance computing systems. As usual, the efficiency of such calculations is based on an interplay of software and hardware that are nowadays moving to hybrid GPU-based technologies. Several well-developed open-source MD codes focused on GPUs differ both in their data management capabilities and in performance. In this work, we analyze the performance of LAMMPS, GROMACS and OpenMM MD packages with different GPU backends on Nvidia Volta and AMD Vega20 GPUs. We consider the efficiency of solving two identical MD models (generic for material science and biomolecular studies) using different software and hardware combinations. We describe our experience in porting the CUDA backend of LAMMPS to ROCm HIP that shows considerable benefits for AMD GPUs comparatively to the OpenCL backend.

We present an optimized implementation of the post-quantum Supersingular Isogeny Key Encapsulation (SIKE) for 32-bit ARMv7-A processors supporting NEON engine (i.e., SIMD instruction). Unlike previous SIKE implementations, finite field arithmetic is efficiently implemented in a redundant representation, which avoids carry propagation and pipeline stall. Furthermore, we adopted several state-of-the-art engineering techniques as well as hand-crafted assembly implementation for high performance. Optimized implementations are ported to Microsoft SIKE library written in “a non-redundant representation” and evaluated in high-end 32-bit ARMv7-A processors, such as ARM Cortex-A5, A7, and A15. A full key-exchange execution of SIKEp503 is performed in about 109 million cycles on ARM Cortex-A15 processors (i.e., 54.5 ms @2.0 GHz), which is about 1.58× faster than previous state-of-the-art work presented in CHES’18.

The problem of transfer from one ALIS (automated library information system) to another is decomposed. The models of ALIS implementation depending of the library’s computerization status are defined; these are fresh implementa-tion; implementation with further data transfer and simultaneous use of the data-base by several ALIS. Various methods of database transport are discussed, i.e. backup recovery; server image porting; tabular data transport through SQL-calls; export-import of bibliographic data and accounts in MARC format. The experience of ALIS databases transport into MegaPro integrated library system on Dubna University Library’s server is examined. The questionnaire-survey for the affiliate University libraries and recommendations for software, backup copying and pro-cedures for data conversion period are presented. Recommendations are also given for choosing the moment of data conversion; the factors for transport model selection and that of in-conversion information losses are specified.

Cloud computing has emerged as an attractive platform for individuals and businesses to augment their basic processing capabilities. Mobile devices with access to Internet are also turning towards clouds for resource-intensive tasks by working out a trade-off between resources required for performing computation on-device against those required for off-loading task to the cloud. However, as with desktop clients, mobile clients face significant concerns related to confidentiality and integrity of data and applications moved to and from the cloud. Cloud-related security solutions proposed for desktop clients could not be readily ported to mobile clients owing to the obvious limitation in their processing capabilities and restrained battery life. We address this problem by proposing architecture for secure exchange and trusted execution between mobile devices and cloud hosts. We establish a symmetric-key-based secure communication channel between mobile and cloud, backed by a trusted coordinator. We also employee a Trusted Platform Module- (TPM-) based attestation of the cloud nodes on which the data and applications of mobile device will be hosted. This gives a comprehensive solution for end-to-end secure and trusted interaction of the mobile device with cloud hosts.

Software radio is a common technique in modern communications equipment, and it is frequently implemented using heterogeneous multicore processors because of its high computational requirements. Programming such systems is still a challenging task and developers rely often on standard parallel APIs and frameworks such as OpenMP and OpenCL. These tools, however, present some limitations when more than one algorithm has to be accelerated. The typical workload of a software radio usually includes several compute-intensive algorithms so it might be still better served by more specific tools, especially on embedded platforms. In this article, a development methodology for implementing software radio applications in heterogeneous multicore embedded platforms is proposed. The methodology is based on GNU radio, a free and open source software toolkit. To validate the methodology, a DVB–T receiver has been ported to an embedded heterogeneous multicore platform as a proof-of-concept. The results show that two different compute-intensive algorithms, Viterbi decoder, and FFT, can be simultaneously accelerated, improving the DVB–T receiver performance by 63%.

Regarding programmable logic controller (PLC) development, improving programming efficiency and encouraging code exchange and software reuse are necessary to increase the productivity and safety of smart manufacturing and industrial automation. However, differences between implementations are significant even though all manufacturers claim to conform to the IEC 61131-3 and IEC 61131-10 standards, resulting in incompatibilities inside heterogeneous systems, preventing projects from interoperating between vendors. In this article, we present an approach that utilizes an ontology-based semantic model named OntoPLC to enable automatic porting of PLC projects between development environments and also prevent significant information loss during the translation process. High-level semantics of PLC projects are added into OntoPLC including software resources, which can be required for software reuse leveraging semantic query. To demonstrate the usefulness of the ontology model, the proposed methodology is applied to a turbine-driven boiler feed pump control module.

The web technology is rapidly increased in various fields. This paper aims to create a server on cloud platform to store data and process the information collected by the air quality monitoring system (AQMS). The monitoring system is developed for transmission and reception of the information received from various data-sources with the use of sensors integrated with microcontroller. The wireless sensing real-time data are transmitted into desired form across the network through internet connection. AQMS is able to monitor concentration of CO2, CO, NO2, temperature and relative humidity and stores the concentration values in the database. This research deals with web service with generous API service, which acts as a messenger for different sensors to monitor the sensed data at cloud network. This process comprises a feature of porting sensed data using Channel ID and read API key assigned by the provider that is able to track data at particular intervals. Front end application is developed and hosted on the cloud platform. Additionally, an App is developed on Android platform to visualize real-time data, which are uploaded in the designed web server, displayed data on the smart phone. MIT App Inventor allows programming to develop mobile applications for Android operating system. An online survey is used to examine the trends of air quality and to gather feedback regarding the undergoing process in the environment. The results of air pollution information indicated that the app supported user’s achievement.

An approach to reproducibility problems related to porting software across machines and compilers.

Porting an existing monolith to a serverless platform ("FaaSification") can be challenging because monoliths commonly have many interdependencies and are highly cohesive. This article introduces a Dependency-Aware FaaSifier (DAF), which allows developers to annotate a method that should be faasified.

This work presents the GPU acceleration of the open-source code CaNS for very fast massively-parallel simulations of canonical fluid flows. The distinct feature of the many-CPU Navier–Stokes solver in CaNS is its fast direct solver for the second-order finite-difference Poisson equation, based on the method of eigenfunction expansions. The solver implements all the boundary conditions valid for this type of problems in a unified framework. Here, we extend the solver for GPU-accelerated clusters using CUDA Fortran. The porting makes extensive use of CUF kernels and has been greatly simplified by the unified memory feature of CUDA Fortran, which handles the data migration between host (CPU) and device (GPU) without defining new arrays in the source code. The overall implementation has been validated against benchmark data for turbulent channel flow and its performance assessed on a NVIDIA DGX-2 system (16 T V100 32Gb, connected with NVLink via NVSwitch). The wall-clock time per time step of the GPU-accelerated implementation is impressively small when compared to its CPU implementation on state-of-the-art many-CPU clusters, as long as the domain partitioning is sufficiently small that the data resides mostly on the GPUs. The implementation has been made freely available and open source under the terms of an MIT license.

With advances in digital technologies, development and verification of DSP audio systems are becoming more and more challenging. Due to high communication requirements introduced with surround audio channel- and latest object-based technologies such as DTS:X and Dolby Atmos, computer's sound card capabilites are expanded with an external audio interface for exchanging high-resolution content between computer and DSP device under test. In this article, the Ethernet TCP/IP-based audio interface solution is proposed. The main idea was to come with the cost-effective communication solution using standard Ethernet IEEE 802.3 hardware, free open-source network stacks, and finally implementing TCP application protocol in point-to-point topology instead of porting custom UDP streaming protocol. Experiments conducted in order to observe overall performance of the system indicate that expected throughput is achieved, but at the cost of long delays and high memory consumption.

International audience; Computing platforms for next-generation cyber-physical systems are evolving towards heterogeneous architectures comprising different processing elements and hardware accelerators. In particular, SoC-FPGA platforms, including multiple general-purpose processing cores tightly coupled with an FPGA fabric, represent an attractive solution due to their flexibility, efficiency, and timing predictability. On these platforms, dedicated hardware accelerators implemented on the FPGA fabric can offload computationally intensive activities from general-purpose processing cores. Furthermore, dynamic partial reconfiguration allows virtualizing the FPGA resources by sharing them among multiple hardware accelerators over time. Although very promising, FPGA-based hardware acceleration also introduces new challenges, such as managing and scheduling multiple concurrent acceleration and reconfiguration requests. The FRED framework has been proposed to address these challenges while preserving the predictability required by real-time systems. FRED is based on a device model that matches the capabilities of contemporary SoC-FPGA platforms and comes with an ad-hoc scheduling infrastructure designed to guarantee bounded response times for DPR-enabled accelerated tasks. This paper presents Fred-Linux, the reference implementation of the FRED framework for GNU/Linux. Fred-Linux allows developing rich applications while leveraging predictable FPGA-based hardware acceleration for performing heavy computations. Fred-Linux has been developed using the Zynq-7000 and Zynq-UltraScale+ by Xilinx as reference platforms, and it can be easily ported and extended on other platforms thanks to its modular design.

PicoRio™ is an open-source project stewarded by the RISC-V International Open Source (RIOS) laboratory—rioslab.org—a nonprofit research lab at Tsinghua-Berkeley Shenzhen Institute (TBSI). The RIOS Lab uses collaborative engineering from both academia and industry to elevate the RISC-V software and hardware ecosystem. In PicoRio, we create an open, affordable, Linux-capable RISC-V hardware platform to aid software developers in porting many modern programs that require Javascript or GPUs. PicoRio will build upon high-quality IPs and software components from expert industry engineers and academic researchers. PicoRio is not proprietary to any specific vendor and platform, and will have complete documentation that can help people to build quality products in a short amount of time. Our plan is to ship PicoRio 1.0 in 1H2021.

A robot’s code needs to sense the environment, control the hardware, and communicate with other robots. Current programming languages do not provide suitable abstractions that are independent of hardware platforms. Currently, developing robot applications requires detailed knowledge of signal processing, control, path planning, network protocols, and various platform-specific details. Further, porting applications across hardware platforms remains tedious. We present Koord—a domain specific language for distributed robotics—which abstracts platform-specific functions for sensing, communication, and low-level control. Koord makes the platform-independent control and coordination code portable and modularly verifiable. Koord raises the level of abstraction in programming by providing distributed shared memory for coordination and port interfaces for sensing and control. We have developed the formal executable semantics of Koord in the K framework. With this symbolic execution engine, we can identify assumptions (proof obligations) needed for gaining high assurance from Koord applications. We illustrate the power of Koord through three applications: formation flight, distributed delivery, and distributed mapping. We also use the three applications to demonstrate how platform-independent proof obligations can be discharged using the Koord Prover while platform-specific proof obligations can be checked by verifying the obligations using physics-based models and hybrid verification tools.

The checkpoint/restart mechanism is critical in a preemptive system because clusters with this mechanism will be improved in terms of fault tolerance, load balance, and resource utilization. As graphics processing units (GPUs) have more recently become commonplace with the advent of general-purpose computation, and open computing language (OpenCL) programs are portable across various CPUs and GPUs, it is increasingly important to set up checkpoint/restart mechanism in OpenCL programs. However, due to the complexity of the internal computational state of the GPU, there is currently no effective and reasonable checkpoint/restart scheme for OpenCL applications. This paper proposes a feasible system, checkpoint/restart state (CRState), to achieve checkpoint/restart in GPU kernels. The computation states including heap, data segments, local memory, stack and code segments in the underlying hardware are identified and concretized in order to establish an association between the underlying level state and the application level representation. Then, a pre-compiler is developed to insert primitives into OpenCL programs at compile time so that major components of the computation state will be extracted at runtime. Since the computation state is duplicated at application level, such OpenCL programs can be preempted and ported across heterogeneous devices. A comprehensive example and ten authoritative benchmark programs are selected to demonstrate the feasibility and effectiveness of the proposed system.

A number of methods have been proposed for suffix sorting on internal memory of RAM and external memory of hard disks. The current best results for suffix sorting on internal or external memory are achieved by several algorithms using the induced sorting (IS) method in various ways. While these algorithms are efficient, the internal ones are much different from those external in terms of the algorithm designs. A scalable IS method that can be applied for suffix sorting on both internal and external memory is highly desired. This article proposes a blockwise IS method to facilitate pipelined access on internal memory and sequential I/Os on external memory. The detailed algorithm of using this method for a 4-stage pipeline with multiple threads is described, where multiple threads are applied to parallelize not only the pipelined stages of consecutive blocks but also the tasks within each stage wherever possible. This algorithm is evaluated by our experiments on a set of realistic and artificial datasets to achieve better overall time and space performance than the existing best results from pSACAK, pDSS and pKS. Beside sorting suffixes on internal memory in linear time, the proposed method can be ported to external memory for sorting massive suffixes in linear I/O complexity.

This essay proposes that computer hacking can provide us with an appropriate framework through which to rethink the basic workings of adaptation in general and Shakespeare adaptation in particular in the twenty-first century. Building on the work of Thomas Leitch and Sarah Cardwell in adaptation studies and Christopher Kelty in the anthropology of the hacker movement, the essay positions itself as an alternative to Douglas Lanier’s model of the Shakespeare rhizome. The central argument is that understanding Shakespeare’s works as source code, and adaptations of them as hacks of that source code, as well as sources of future hacks, makes it possible to account for and work with the difficult but crucial notions of the source and of fidelity, while resolving many of the theoretical, practical, and political problems which motivated scholars to avoid or try to overcome those notions in the past.

In this article, we are interested in the implementation of an open-source low-level architecture (critical system) adapted to agile and easily replicable close-range remote sensing robots operating in multiple evolution domains. After reviewing the existing autopilots responding to these needs, we discuss the available hardware solutions and their limits. Then, we propose an original solution (software and hardware) that we developed to obtain a universal low-level architecture for all our exploration robots, whatever their environment of evolution, and the steps needed to make it run on our chosen family of micro-controllers: the ESP32. Finally, we present the operational results obtained on our different platforms (land, surface, submarine and air), their limits and the envisaged perspectives.