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Three-dimensional (3D) interconnection technology offers several electrical advantages, including reduced signal delay, reduced interconnect power, and design flexibility. 3D integration relies on through-silicon vias (TSVs) and the bonding of multiple active layers to stack several die or wafers containing integrated circuits (ICs) and provide direct electrical interconnection between the stacked strata. While this approach provides several electrical benefits, it also offers significant challenges in thermal management. While some work has been done in the past in this field, a comprehensive treatment is still lacking. In the current work, analytical and finite-element models of heat transfer in stacked 3D ICs are developed. The models are used to investigate the limits of thermal feasibility of 3D electronics and to determine the improvements required in traditional packaging in order to accommodate 3D ICs. An analytical model for temperature distribution in a multidie stack with multiple heat sources is developed. The analytical model is used to extend the traditional concept of a single-valued junction-to-air thermal resistance in an IC to thermal resistance and thermal sensitivity matrices for a 3D IC. The impact of various geometric parameters and thermophysical properties on thermal performance of a 3D IC is investigated. It is shown that package and heat sink thermal resistances play a more important role in determining temperature rise compared to thermal resistances intrinsic to the multidie stack. The improvement required in package and heat sink thermal resistances for a 3D logic-on-memory implementation to be thermally feasible is quantified. An increase in maximum temperature in a 3D IC compared to an equivalent system-in-package (SiP) is predicted. This increase is found to be mainly due to the reduced chip footprint. The increased memory die temperature in case of memory-on-logic integration compared to a SiP implementation is identified to be a significant thermal management challenge in the future. The results presented in this paper may be useful in the development of thermal design guidelines for 3D ICs, which are expected to help maximize the electrical benefits of 3D technology without exacerbating thermal management issues when implemented in early-stage electrical design and layout tools. [ABSTRACT FROM AUTHOR]

The mechanical integrity of low-k dielectric films has brought many process challenges in both front-end integration and back-end assembly, mostly due to possible interfacial delamination and fractures within the low-k films. From a packaging point of view, it is important to have an assessment of the integrity of the low-k stack before the device is fully assembled and the time-consuming full package evaluation is started. Some of the methods that are presently used to evaluate devices with low-k films either do not reflect the real stress situation in a package (such as 4-point bend), or introduce a mixed die-solder failure mode (such as die pull), which makes the results hard to interpret. In this paper, an evaluation method using solder bump shear is introduced. The solder joints are electroplated with a Cu stud as part of the under bump metallization. When the testing parameters are carefully optimized, bump shear can induce a failure in the low-k stack. By analyzing the maximum load of the shear test and the characteristics of the load curves, die with different interlayer dielectric materials and locations on the die with different interconnect metal densities can be effectively differentiated. A finite-element model is established and fracture mechanics methodologies are utilized to interpret the results of the bump shear. [ABSTRACT FROM AUTHOR]