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This paper presents novel power-efficient designs of quaternary logic gates like Quaternary Minimum (QMIN) and Quaternary Maximum (QMAX), Standard Quaternary Inverter (SQI), Standard Quaternary NAND (SQNAND), Standard Quaternary NOR (SQNOR) and Standard Quaternary XOR (SQXOR) using Carbon Nanotube Field Effect Transistor (CNTFET). The designs are based on Pass Transistor Logic (PTL) and use only three types of Carbon Nanotube (CNT) diameters 0.626 nm, 1.018 nm, and 2.27 nm, which lead to lower fabrication costs and enhanced manufacturability when compared to the state-of-the-art designs. The designs are simulated in HSPICE with a 32 nm CNTFET model provided by Stanford University, and the average power and maximum propagation delay obtained from the simulation results are compared with other existing designs. It shows that the proposed designs require 75% to 90% less power and they achieve 73% to 91% less Power Delay Product (PDP) than the latest designs. [ABSTRACT FROM AUTHOR]

In this paper, a simple carbon nanotube field effect transistor (CNTFET)-based inverter has been simulated and the impacts of changing various design and process parameters on its characteristics and performance have been analysed using HSPICE. The 32 nm CNTFET model of Stanford University has been used here for the simulation of the inverter. The simulation results and the voltage transfer characteristics (VTC) curve of the inverter have been extracted for (i) different channel lengths, (ii) top gate di-electric material thickness (tox), (iii) pitch value (iv) the number of tubes in CNTFET channel region and (v) chirality of the CNT. It has been observed that the VTC curve changes significantly with different values of these parameters. Some important output parameters like maximum dc current, power, rise time, fall time, average propagation delay, etc. have been measured in each case. Changes in maximum power consumption value due to the change in different parameter values are observed through plotted graphs. Output dc current vs. input voltage graphs have been plotted for different chirality of the tubes, the number of the tubes, and pitch values between n-type CNTFET and p-type CNTFET of the inverter. [ABSTRACT FROM AUTHOR]

This paper presents a novel power and energy-efficient carbon nanotube field-effect transistor (CNTFET)-based design of a quaternary magnitude comparator for single and double digits. It also proposes an improved circuit of the ternary single-digit comparator and a novel design of the double-digit ternary comparator. The designs make use of the pass transistor logic and transmission gates, resulting in a more power and energy-efficient design with a lower number of CNTFETs when compared with existing designs. Besides, this paper also proposes a generalized circuit of magnitude comparator for multiple digits. The proposed circuits are simulated in HSPICE using the 32 nm CNTFET model presented by Stanford University. Average power and propagation delays are observed and the power-delay-product (PDP) is calculated in each case. The impact of process parameter variations has been analyzed through Monte Carlo simulation and has been presented in the form of two-dimensional graphs. [ABSTRACT FROM AUTHOR]

This paper presents designs of ternary and quaternary up/down counters of single and multiple digits using CNTFET. The proposed counters have a special feature of counting in dual mode; up counting and down counting which makes these designs distinct from other existing designs. The proposed counters are designed using ternary/quaternary D flip-flops and a dynamic successor-predecessor circuit. The D flip-flops are built using standard ternary/quaternary inverters (STI/SQI) with an additional reset feature. The proposed dynamic successor-predecessor circuit has the capability of acting either as a successor or as a predecessor circuit based on a control signal. Counter circuits of multiple digits have been achieved with the help of a few additional transistors along with the single-digit counter circuits. All the proposed designs have been simulated in HSPICE using Stanford University's 32 nm CNTFET model and simulation results have been noted. When compared with existing designs, the proposed designs show improvements in power and energy efficiency. [ABSTRACT FROM AUTHOR]

This paper presents a miniature-size band-reject filter on a Coplanar Waveguide (CPW) transmission line using series connected complementary split ring resonators (CSRRs) and series capacitive gaps for X-band applications. The band-reject filter has highly miniaturized dimensions and is capable of solving almost all the basic limitations to which the conventional band-reject filters are mostly susceptible. The series connected CSRRs are etched on the signal planes of the CPW transmission line on silicon substrate enabling CMOS compatibility with planar IC technology. It is a concept resulting in higher bandwidth, low insertion loss of 0.5 dB with high rejection of 40 dB in the stop bands better than similar designs. The optimized design of the proposed device is performed using the parametric study of filter characteristics. The proposed devices RF analysis and circuit model are simulated using Ansoft High-Frequency Structural Simulator (HFSS) v13® and Agilent Advanced Design System (ADS) 2009. Measured results are in good agreement with their simulated counterparts and the measured performance is encouraging in all respects. [ABSTRACT FROM AUTHOR]

In this paper, we report the comparative study of some parameters of II–VI ternary alloy ZnCdTe and II–VI–O dilute oxide ZnCdTeO. The purpose of this comparative study is to establish both the ternary and quaternary alloys as superior materials for optoelectronic and solar cell applications in which the quaternary materials show more superiority than the ternary material. In this purpose, we take the data from the experiments previously done and published in renowned journals and books. The parameters of these alloys are mainly being calculated using Vegard's law and interpolation method of those collected data. It was certainly demonstrated that the incorporation of O atoms produces a high bandgap (Δ E g ) reduction in host ZnCdTe (Zn 1 − x CdxTe) in comparison to the bandgap reduction in host ZnTe material with Cd incorporation. The bandgap of ZnCdTeO (Zn 1 − x CdxTe 1 − y Oy) was found to be reduced to 1.1357 at x = y = 0. 5 and the spin–orbit splitting energy ( Δ SO ) value of ZnCdTeO was calculated to be 1.175 eV for Cd concentration of 0.5 mole and O concentration of 0.1 mole both of which showed excellent results with the prospect of optoelectronic and solar cell applications. The constant rise in the spin–orbit curve signifies a very less internal carrier recombination which decreases the leakage current and augments the efficiency of solar cell. The lattice constants and strain calculation values give very good results and confirm the stability of the materials. Besides, the calculated band offsets values show that for ZnCdTeO, there is higher bandgap reduction than that of ZnCdTe. Moreover, ZnCdTeO covers a wide range of wavelength in the visible region starting from violet region at 393 nm upto red region at 601 nm. Both ZnCdTe and ZnCdTeO are found to have excellent applications in optoelectronic and solar cell devices though quaternary ZnCdTeO proves much supremacy over ternary ZnCdTe in all aspects of the properties. [ABSTRACT FROM AUTHOR]

The design of a metamaterial-based tunable band elimination filter is described on silicon coplanar wave- guide (CPW) using complementary split ring resonators (CSRRs) and radio frequency microelectromechanical systems (MEMS) varactors to ensure compatibility with integrated circuit fabrication technology. CSRRs are patterned on both the active signal line and ground on both sides. A cantilever bridge is suspended on the signal line to realize variable capacitance. The rejection band of the filter is tuned by moving the MEMS bridge up or down using electrostatic actuation. A stopband around the center frequency of 35.32 GHz with a rejection ratio of $\sim 20.19$ dB is obtained when the bridge is pulled down. Another stopband around the center frequency 38.80 GHz is observed with a rejection ratio of $\sim 18.29$ dB when the bridge is allowed to remain in its up state without electrostatic actuation. Simulation for RF behavior is performed using ANSOFT High Frequency Structural Simulator v13. Numerical extraction of the filter parameters has been done using Agilent ADS (2009) and COVENTORWARE (2010) for mechanical and electromechanical characterization. This is the first reported tunable CPW filter having CSRR on the signal line and ground plane on silicon substrate using MEMS technology. [2014-0365] [ABSTRACT FROM PUBLISHER]

Abstract: A band reject filter with tuning capability is presented on a CPW transmission line on silicon substrate using comb line and RF MEMS variable capacitor, enabling compatibility with planar IC technology. A conventional CPW on a substrate consists of a central strip conductor with semi-infinite ground planes on either side. A comb line is etched on the signal line of the CPW and the MEMS bridge capacitor is put on the same line in shunt. Tunability of the filter is achieved by putting the MEMS bridge in either up or down state. The rejection at the centre frequency of stop bands are around −40.24dB for down state and −38.21dB for up state of the bridge. A low insertion loss, as low as −0.68dB, is obtained in the pass band. The proposed device structure is simulated using ANSOFT HFSS v13® for RF analysis and COVENTORWARE (2008)® for mechanical and electromechanical characterization, both static and transient analysis. [Copyright &y& Elsevier]