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Scaled ferroelectric transistors (L g =76 nm) in a back- gated configuration are fabricated with a channel-last process flow. Using this approach, optimization of the ferroelectric gate oxide film can be decoupled from that of the semiconductor channel to reduce parasitic interfaces. As a result, ferroelectric transistors with 3σ memory window for fast programming time of 10 ns (including an instantaneous read-after-write) at 1.8 V and high endurance of 1012 cycles are demonstrated for the first time.

The performance and reliability of (1 0 0) and (1 1 0) sidewall, silicon-on-insulator (SOI) FinFETs with a Hf-based gate dielectric were evaluated. Unlike the typical planar MOSFET mobility orientation dependence, (1 1 0) FinFET sidewalls do not impair electron mobility and result in good short channel performance compared to (1 0 0) FinFET sidewall devices. Hot carrier injection (HCI) degradation was also investigated with nMOS and pMOS high-κ FinFETs on both sidewall surface orientations. Impact ionization at the source, as well as at the traditional drain side, was found to enhance HCI degradation when gate voltage ( V g ) = drain voltage ( V d ). The degradation becomes more pronounced as the gate length decreases, with a negligible dependence on substrate orientation. However, the orientation dependence of negative bias temperature instability (NBTI) on FinFETs demonstrates that the (1 1 0) orientation is slightly worse than (1 0 0). The kinetics of Δ N IT ( t ) under negative bias stress conditions suggests the interface trap density ( N IT ) is generated by a mechanism similar to that in planar devices.

Thermally robust Ni germanide (NiGe) using the cosputtering of Ni and Pt on Ge-on-Si substrate is proposed for high-performance nanoscale germanium metal-oxide-semiconductor field-effect transistors (Ge MOSFETs). The rapid thermal process temperature window for the stable sheet resistance of the proposed Ni-Pt cosputtered structures was about 50-100°C wider than that of the pure Ni structure, with neither NiGe agglomeration nor local penetration of Ni atoms into the substrate. In addition, the surface and interfacial morphologies of the Ni-Pt cosputtered structure were much smoother and more continuous than those of a pure Ni structure. The improvement in the thermal stability was attributed to the change of the crystal structure due to the suppression of the diffusion of Ni atoms and the uniform distribution of Pt atoms. Therefore, this proposed Ni-Pt cosputtered structure could be promising for high-mobility Ge-on-Si MOSFET applications.

The continued scaling of CMOS devices to the sub-16 nm technology node will likely be achieved with new architectures, such as FinFETs and high mobility substrates, including compound semiconductors (III-V). At these technology nodes, abrupt channel doping profiles with high dopant activation will be needed under low thermal budget environments for III-V materials. Ion implantation into III-V materials presents a problem as it induces crystal damage, which can alter the stoichiometry in a manner that is difficult to recover. The residual damage can lead to higher junction leakage and lower dopant activation. This paper presents a potentially defect-free alternative, mono-layer doping (MLD), which utilizes wet processing techniques.

Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.

Planar band-to-band tunneling FETs (TFETs) have been fabricated on silicon-on-insulator (SOI) substrates using conventional CMOS technologies with a highly scaled sub-60 nm gate length (effective gate length [ L g ] ∼ 40 nm due to an overlap between the source and gate) and different anneal sequences. The optimal anneal sequence including spike and flash annealing resulted in a drive ON current ( I ON) ) > 100 μA/μm with I ON /I OFF > 10 5 at a drain bias of −1 V. The devices exhibited negative differential resistance and non-linear subthreshold temperature dependencies, consistent with the band-to-band tunneling mechanism. Simulations using a 2-D TCAD simulator, MEDICI, agreed with experimental data, demonstrating the possibility of Si tunnel transistors in logic applications.

Preserving the integrity (e.g., Ge concentration, strain, and lattice perfection) of pseudomorphically grown silicon germanium (SiGe) heterostructure channels on Si substrates is one of the most critical factors in obtaining optimal pMOSFET performance from high hole mobility of strained SiGe. A millisecond Flash-assisted rapid thermal annealing (RTA) technique was applied to source/drain (S/D) dopant activation of high-Ge-concentration SiGe channel MOSFETs with a high-k/metal gate stack. Flash annealing of SiGe channel pMOSFETs is shown to be an effective way to preserve channel integrity while achieving a low S/D resistance. Excellent mobility and short-channel device performance are realized. In addition, as the concentration of Ge in the SiGe layer is increased, high B activation can be achieved with a lower peak temperature Flash anneal. As a result, the sheet resistance of the implanted p+ junction can be comparable with that of higher temperature Flash-annealed (or optimal spike-annealed) Si. Furthermore, minimizing Ge diffusion reduces performance variation (such as statistical threshold voltage variation), which may be caused by the introduction and/or growth of defects in the strained SiGe heterostructure channel. It is shown that high-performance SiGe channel pMOSFETs with high Ge concentrations and a scaled high- k/metal gate can be achieved by a millisecond Flash-assisted RTA technique while preventing undesirable effects in the SiGe channel, such as within-wafer statistical performance variation.

Accurate extraction of the Schottky barrier height (SBH) is imperative to the development of low-resistance contacts. Nonlinearity in the Richardson plot generates errors in the extraction of the SBH. Without invoking generation-recombination currents, defect-assisted tunneling, or even inhomogeneity, nonlinearity of the Richardson plot can be explained by thermionic field emission (TFE) and can be evidenced even in lightly doped diodes. An analytical model is proposed whereby the extracted barrier height is actually related to the peak energy of the energy distribution of the emitted electrons and can be extracted from a typical Richardson plot using polynomial regression. A comparison of the proposed model with the conventional model and a popular inhomogeneous model that uses a Gaussian distribution of barrier heights concludes that the proposed TFE model extends the doping range of an accurate extraction of the SBH.

The superior transport properties of III-V materials makes them attractive choices to enable improved performance at low power. This paper examines the module targets and challenges for III-V materials to be successfully integrated for high performance/low power logic at or beyond the 11 nm technology node. A VLSI compatible, self-aligned, III-V on 200mm Si MOSFET process flow is presented using an industry standard toolset. Statistically significant data shows that III-V devices can be processed on a Si line with controlled contamination, good uniformity and yield. The Lg = 500 nm device has a drive current of 471 µA/µm (Vgs = Vds = 1V) and intrinsic transconductance of 1005 µS/um.

pMOSFET performance of high Ge content (~50%) biaxial compressive strained SiGe heterostructure channel pMOSFETs is characterized, and performance between 〈110 〉 and 〈100 〉 channel orientations on a (001) substrate is compared for physical channel lengths down to ~80 nm. Temperature-dependent mobility and velocity are characterized for both channel directions. First, it is shown that high Ge content SiGe-based channels can deliver drive current enhancement over unstrained Si below sub-100-nm channel lengths. Second, it is found that, with a higher Ge content SiGe channel under biaxial compressive strain, there is a difference of drive current between 〈110 〉 and 〈100 〉 channel directions, and the difference increases when temperature is lowered and/or when channel length is scaled down. An external series resistance difference is detected between two channel directions, although it appears to be insufficient to explain all the direction-dependent drive current difference. Channel transport behavior in different channel orientations can be clearly observed with low external source/drain (S/D) series resistance achieved with a millisecond S/D dopant activation anneal process while controlling the thermal budget. Two possibilities have been investigated to understand channel-direction-dependent performance: possible differences in effects of device processing impact between two channel directions and anisotropic transport effects from an anisotropic hole band structure, particularly under biaxial compressive strain in a SiGe channel pseudomorphically grown on a Si substrate.

The self-gain of surface channel compressively strained SiGe pMOSFETs with HfSiOx/TiSiN gate stacks is investigated for a range of gate lengths down to 55 nm. There is 125% and 700% enhancement in the self-gain of SiGe pMOSFETs compared with the Si control at 100 nm and 55 nm lithographic gate lengths, respectively. This improvement in the self-gain of the SiGe devices is due to 80% hole mobility enhancement compared with the Si control and improved electrostatic integrity in the SiGe devices due to less boron diffusion into the channel. At 55 nm gate length, the SiGe pMOSFETs show 50% less drain induced barrier lowering compared with the Si control devices. Electrical measurements show that the SiGe devices have larger effective channel lengths. It is shown that the enhancement in the self-gain of the SiGe devices compared with the Si control increases as the gate length is reduced thereby making SiGe pMOSFETs with HfSiOx/TiSiN gate stacks an excellent candidate for analog/mixed-signal applications.

In this paper, we focus on the performance of a nanowire Field Effect Transistor (FET) in the Ultimate Quantum Capacitance Limit (UQCL) (where only one subband is occupied) in the presence of interface traps ($D_{it}$), parasitic capacitance ($C_L$) and source/drain series resistance ($R_{s,d}$) using a ballistic transport model and compare the performance with its Classical Capacitance Limit (CCL) counterpart. We discuss four different aspects relevant to the present scenario, namely, (i) gate voltage dependent capacitance, (ii) saturation of the drain current, (iii) the subthreshold slope and (iv) the scaling performance. To gain physical insights into these effects, we also develop a set of semi-analytical equations. The key observations are: (1) A strongly energy-quantized nanowire shows non-monotonic multiple peak C-V characteristics due to discrete contributions from individual subbands; (2) The ballistic drain current saturates better in the UQCL compared to CCL, both in presence and absence of $D_{it}$ and $R_{s,d}$; (3) The subthreshold slope does not suffer any relative degradation in the UQCL compared to CCL, even with $D_{it}$ and $R_{s,d}$; (4) UQCL scaling outperforms CCL in the ideal condition; (5) UQCL scaling is more immune to $R_{s,d}$, but presence of $D_{it}$ and $C_L$ significantly degrades scaling advantages in the UQCL., Comment: Accepted at IEEE Transactions on Electron Devices

We report on the promise of using SiGe channel FinFETs for high performance CMOS for the sub-22nm node. Devices with Si, stacked SiGe/Si, shell/core SiGe/Si and homogeneous SiGe fins with (110) and (100) surface orientations were fabricated and characterized. The stacked SiGe/Si fin device exhibited a dual turn-on due to the SiGe and Si regions. The shell/core SiGe/Si fin device mobility was 30% greater than the Si fin. The homogeneous SiGe fin device with a (110) orientation had a mobility 3.6X higher than the Si fin device with a (100) orientation.

In this paper, thermally stable Ni germanide using a Ni-Pt(1%) alloy and TiN capping layer is proposed for high-performance Ge MOSFETs. The proposed Ni-Pt(1%) alloy structure exhibits low-temperature germanidation with a wide temperature window for rapid thermal processing. Moreover, sheet resistance is stable and the germanide interface shows less agglomeration despite high-temperature postgermanidation anneal up to 550 °C for 30 min. In addition, the surface of the Ni-Pt(1%) alloy structure is smoother than that of a pure Ni structure both before and after the postgermanidation anneal. Only the NiGe phase and no other phases such as PtxGey and NixPt1-xGey can be observed in X-ray diffraction results, but X-ray photoelectron spectroscopy shows that PtGe is formed during the postgermanidation anneal. The larger Pt atomic radius is believed to inhibit the diffusion of Ni into the Si substrate, thereby improving the thermal stability of the NiGe. The higher melting point of PtGe is also believed to improve thermal stability. Therefore, this proposed Ni-Pt(1%) alloy could be promising for high-mobility Ge MOSFET applications.

Scaling of complementary metal oxide semiconductor devices is critical to enhancing performance and reducing the production cost of transistors. Conventional gate stack film systems consisting of a SiO2 dielectric layer between the Si substrate channel and a doped polycrystalline silicon (poly-Si) gate electrode exhibited excessively high gate current leakage when the physical thickness of this traditional dielectric was scaled to Tphys = ∼2 nm. The rate of scaling was initially preserved by incorporating nitrogen to form an SiOxNy insulator layer; however, this material soon experienced unacceptable levels of direct tunneling leakage current, which launched an industry-wide investigation of potential high dielectric constant (high-k) metal oxides as replacement materials for the SiO2 based gate dielectric layer. Thermal stability requirements for the introduction of high-k dielectric materials necessitated the simultaneous replacement of poly-Si with a metal gate electrode due to several performance factors including unscalable threshold voltage. Although high-k/metal gate thermal stability has been demonstrated, significant challenges remain to be resolved for future technology nodes. This paper reviews the progress and challenges associated with the introduction of high-k/metal gate transistors, including threshold voltage tuning and gate dielectric thickness scaling, from a materials and process integration perspective.

The short-channel performance of compressively strained Si0.77Ge0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe.

Hydrogen (H) ion shower doping was proposed to improve the thermal stability of nickel germanide (NiGe), and its effects were analyzed in depth. As the post-germanidation annealing temperature was increased, the sheet resistance (Rsh) of the undoped sample increased sharply due to NiGe agglomeration while that of the H-doped samples showed a little increase at a temperature above 550 ◦C due to the suppression of NiGe agglomeration and Ni penetration. Hydrogen atoms in NiGe were found to significantly suppress local penetration of Ni atoms out of NiGe and hence contribute to the improvement the thermal stability of NiGe.

This paper discusses recent progress in and challenges of threshold voltage control for advanced high-k/metal-gated (HKMG) devices. It presents the impact on threshold voltage (V"t) control of incorporating La and Al into HKMG devices. A dipole moment model explaining V"t tuning of HfSiON/metal-gated MOSFETs is proposed. In addition, a dual channel scheme that allows La"2O"3 capping in NMOS and a SiGe channel in PMOS to achieve acceptable V"t for HKMG CMOS devices will be discussed. Also shown is the impact of the robustness of the SiO"2/Si interface on the HKMG MOSFET V"t-equivalent oxide thickness (EOT) roll-off. Finally, techniques to improve the interface quality of a HKMG stack will be discussed.

An interface dipole model explaining threshold voltage (Vt) tuning in HfSiON gated n-channel field effect transistors (nFETs) is proposed. Vt tuning depends on rare earth (RE) type and diffusion in Si/SiOx/HfSiON/REOx/metal gated nFETs as follows: Sr < Er < Sc+Er < La < Sc < none. This Vt ordering is very similar to the trends in dopant electronegativity (EN, dipole charge transfer) and ionic radius (r, dipole separation) expected for a interfacial dipole mechanism. The resulting Vt dependence on RE dopant allows distinction between a dipole model (dependent on EN and r) and an oxygen vacancy model (dependent on valence).

The effects of a Si capping layer on the device characteristics and negative bias temperature instability (NBTI) reliability were investigated for Ge-on-Si pMOSFETs. A Ge pMOSFET with a Si cap shows a lower subthreshold slope (SS), higher transconductance (G"m) and enhanced drive current. In addition, lower threshold voltage shift and G"m","m"a"x degradation are observed during NBTI stress. The primary reason for these characteristics is attributed to the improved interface quality at the high-k dielectric/substrate interface. Charge pumping was used to verify the presence of lower density of states in Ge pMOSFETs with a Si cap.

Highly thermally stable Ni germanide technology for high performance germanium metal-oxide-semiconductor field-effect transistors (Ge MOSFETs) is proposed, utilizing Pd incorporation into Ni germanide. The proposed Ni germanide shows not only the improvement of thermal stability but also the reduction of hole barrier height, which can improve the device on-current by reducing the Ni germanide to p+ source/drain contact resistance. The proposed Ni germanide showed a stable sheet resistance of up to 500degC 30-min postgermanidation annealing due to the suppression of agglomeration and oxidation of Ni germanide and the diffusion of Ni and Ge atoms by the incorporated Pd. Therefore, the proposed Ni0.95Pd0.05 alloy could be promising for the high mobility Ge MOSFET applications.

We demonstrated the effect of post-metallization annealing and Si interlayer thickness on Ge MOS capacitor on Ge-on-Si substrate with HfO2/TaN. Ge outdiffusion and oxygen interdiffusion were completely suppressed by thick Si interfacial layer. As a result, formation of insufficient low-k Ge oxides was effectively inhibited. It is confirmed that gate current of Si passivated Ge MOS was decreased by Si IL and decrease of gate current, Jg is saturated after Si IL of 2 nm. It was also observed that when Si IL is thick enough to restrict Ge outdiffusion, increase of Jg is not due to the temperature-induced Ge outdiffusion but due to the partial crystallization of HfO2 at higher annealing temperature.

The advent of high-k/metal gates into production for CMOS gate stacks has marked the onset of MOSFET scaling that has clearly become reliant on new materials and / or new device architecture. Additionally, new approaches to form ultra-shallow junctions with high active-dopant concentrations and low schottky barrier height silicides with novel materials to reduce contact resistance have been reported by many groups and will continue to facilitate MOSFET scaling with increasing performance. It is becoming clear that Si (as the channel) may not be able to provide for the high performance combined with low power technologies that would be needed in future. Over several years, there has been a lot of research on high mobility channels: group IV for pMOSFETs and III-V for NMOSFETs. However, there appears to be little consensus on a) the choice of high mobility channels for P and N channel MOSFETs, b) its potential compared to short channel strained-Si, and 3) potential technology node for insertion. In this work, trends, challenges and opportunities related to several of the aforementioned modules (gate stack, junctions, contacts, and high mobility Ge based channels) will be briefly presented and discussed.

High-performance sub-60 nm Si/SiGe (Ge:~75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first high-kappa/metal gate stacks with ~1 nm equivalent oxide thickness, are demonstrated. For the first time, short gate length (L g) devices demonstrate not only controlled short channel effects, but also an excellent on-off current (I on/I off) ratio (~5times104 55-nm L g). The intrinsic gate delay of these heterostructures is ~3 ps at I on/I off~104. OFF-state leakage was minimized by controlling the defects in the epitaxial films. Finally, these short L g devices, when benchmarked against state-of-the-art Si channel pMOSFETs, appear to be very promising in replacing the Si channel in CMOS scaling.

Electrical characteristics of metal–oxide–semiconductor (MOS) capacitors and transistors fabricated on Ge epitaxial layers exhibit a strong dependence on layer structures, such as the Ge epitaxial layer thickness, Si cap layer, and Ge channel doping. The dependence in Ge-on-Si devices is associated with different material parameters of epitaxial Ge layers and Si substrates, such as bandgap energy (Eg), intrinsic carrier concentration (ni), and permittivity (e). The flat band voltages of capacitors are independent of the thickness of epi-Ge layer grown on Si substrates. The threshold voltages, however, exhibit strong dependency on layer structures. Non-ideal capacitance–voltage characteristics, such as low frequency behavior and frequency dispersion, are also determined by combined effects of Ge-on-Si heterostructures.

The authors report on interface characteristics of ZrO2 high-k gate dielectrics on Ge epitaxial layers integrated on Si substrates. For surface passivation, thermal desorption of Ge native oxide and Ge nitridation processes is applied to epitaxial Ge capacitor layers. Metal-oxide-semiconductor capacitors exhibit excellent electrical characteristics with a gate leakage current density of 6 × 10− 7–1 × 10− 6 A/cm2 with a capacitance equivalent thickness of 1.5–1.3 nm at a gate voltage of 1 V. Thermal behavior of Ge native oxide and nitrided Ge layers is correlated with electrical characteristics.

A review of literature combined with recent experimental results addressing the intrinsic and extrinsic factors controlling the effective work function (EWF) of metal gate electrodes on Hf-based high-K dielectrics is discussed. Through a systematic study including accurate extraction of EWF, our observations suggest, unlike popularly perceived, intrinsic E"f-pinning does not limit the EWF tuning on high-K. Also, a critical issue challenging the maintenance of high EWF metals at low effective oxide thicknesses (EOT), due to a new phenomena described as the ''V"f"b roll-off'', is reported for the first time.

A degradation of low field mobility has been widely reported for HfO2/TiN gate MOSFETs [1, 2]. It has recently been demonstrated that interface defect densities in the range 3-4x10cm do not yield significant mobility degradation [3, 4]. However, as with conventional polySi/SiO2 MOSFETs, interface state generation and mobility degradation do occur for HfO2/TiN gate MOSFETs under negative bias temperature stress [5, 6]. Previous work has demonstrated a relationship between mobility and fixed oxide charge for stressed n channel HfO2/TiN gate MOSFETs [7]. In this work we extend the results reported in [7] to investigate the relationship of effective mobility (μeff) and interface defect density (Dit) for both n and p channel HfO2/TiN gate MOSFETs, based on negative-biastemperature stress of the gate oxide. From the relationship of μeff to Dit the associated scattering parameter (α) is determined for n and p channel HfO2/TiN MOSFETs.

The influence of substrate heterostructure (Si/ SiGe/ Si) on performance of MOSFETs with high-k/metal gate stacks has been studied. In particular, the effects of the channel thickness on the performance and short channel properties are evaluated. It is found that these heterostructures, when designed optimally, can not only exhibit high mobility but also excellent control of short channel effects down to 70 nm gate length.

The influence of HfO"2 thickness (1.6 to 3nm) on interface state density and low field mobility in HfO"2/TiN gate n channel MOSFETs have been studied by analyzing experimental data from charge pumping, split CV, DC I"d-V"g, pulsed I"d-V"g and Y-function methods. It is found that there is no HfO"2 thickness dependence on the interface state density, whereas there is continuous electron mobility degradation with HfO"2 thickness. The devices exhibited no detectable fast transient charge trapping, allowing the relative contributions of phonon and Coulomb scattering to be examined over temperature. The dependence of the low field mobility on temperature from 50 K to 400 K indicates HfO"2 remote phonon scattering as the dominant cause of the mobility degradation.

To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiOX passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332 cm2 middotV-1middots-1 at 0.05 MV/cm-a 2times enhancement over the universal Si/SiO2 mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an ION/IOFF ratio of 3times103 without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface

The effect of device fabrication temperature on the work function of ruthenium (Ru) metal gate and its bilayers was investigated. The work function shows strong temperature dependence when Ru electrodes are deposited on silicon oxide, SiO 2 , but not on hafnium silicates (HfSiO x ). Specifically, the work function of Ru on SiO 2 increased from 4.5 eV at 500 °C to 5.0 eV at 700 °C. On further annealing to 900 °C or higher, the work function dropped to about 4.4 eV. In the case of HfSiO x , the work function of Ru changed by less than 100 mV over the same temperature range. Identical temperature dependence was observed using hafnium (Hf)/Ru and tantalum (Ta)/Ru bilayers. However, the peak values of the work function decreased with increasing Hf/Ru and Ta/Ru thickness ratios. Materials analysis suggests that these trends are driven by interactions at the Ru metal gate–dielectric interface.

This letter correlates fast transient charging (FTC) in high-k gate dielectrics to variations in its oxygen content. Analysis of electrical and physical data suggests that the observed enhancement of FTC may be caused by reduction of the oxygen content in the high-k film due to O scavenging process induced by the HfSix metal electrode. A hypothesis correlating O scavenging from the high-k dielectric to O vacancy formation, which contributes to FTC, is proposed

The optimization of MOSFET performance with Hf-based high-k and TiN metal gate is discussed. MOSFET performance and mobility of metal and poly gate on both high-k and SiO2 are compared. Optimization of the thickness and composition of Hf-silicate is discussed in terms of charge trapping and boron diffusion. The effect of metal gate thickness is also investigated. Appropriate dry and wet etch processes are found to effectively eliminate the metal foot and high-k undercut. Impressive Ion- Ioff characteristics have been achieved by applying an optimized gate-first CMOS flow to the high-k/metal stack. Ion = 1100µA/µm and 540µA/µm was attained for N and PMOSFETs with Vdd = 1.2V and Ioff = 100nA/µm.

Atomic layer deposited (ALD) Hf-based dielectrics have been studied to understand scaling, electron mobility, and threshold voltage stability issues in transistor devices. ALD HfO2 formed from TEMAHf and O3 was found to reach a scaling limit near Tphys=1.2 nm. Knowledge of this limit is important because mobility improvements are observed as HfO2 is scaled to 2.0 nm and below. Concurrent with mobility improvement, a reduction in transient charging is manifested as improved VTH and Id stability during constant voltage stress. HfO2 attributes include the following: EOT=1.0 nm, >100× Jg reduction vs. SiO2/PolySi, high field mobility of 82% universal SiO2 and ~20 mV of DVTH after 1000s stress at 1.8V. Similar results can be obtained for (HfO2)x(SiO2)1-x alloys. These results suggest that high-k dielectrics can be competitive with the current gate dielectric material SiON.

The effective work function (EWF) extracted on terraced oxide structures by capacitance-voltage-based techniques was compared with the work function calculated from the barrier height extracted by current-voltage measurements. The results show a reasonable correlation-within /spl plusmn/ 0.1 eV-in the EWF values for various metal gate electrodes, validating both techniques for EWF extraction.

Issues surrounding the integration of Hf-based high-/spl kappa/ dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate-stack process as well as optimization of other CMOS process steps enable robust metal/high-/spl kappa/ CMOSFETs with wide process latitude. HfO/sub 2/ of a 2-nm physical thickness shows a very minimal transient charge trapping resulting from kinetically suppressed crystallization. Thickness of metal electrode is also a critical factor to optimize physical-stress effects and minimize dopant diffusion. A high-temperature anneal after source/drain implantation in a conventional CMOSFET process is found to reduce the interface state density and improve the electron mobility. Even though MOSFET process using single midgap metal gate addresses fundamental issues related to implementing metal/high-/spl kappa/ stack, integrating two different metals on the same wafer (i.e., dual metal gate) poses several additional challenges, such as metal gate separation between n- and pMOS and gate-stack dry etch. We demonstrate that a dual metal gate CMOSFET yields high-performance devices even with a conventional gate-first approach if an appropriate metal separation between band-edge metal for nMOS and pMOS is incorporated. Optimization of dry-etch process enables gentle and complete removal of two different metal gate stacks on ultrathin high-/spl kappa/ layer.

Issues surrounding the integration of Hf-based high-k dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate stack process as well as optimization of other CMOS process steps enables robust CMOSFETs with a wide process latitude. HfO2 of a 2 nm physical thickness shows complete suppression of transient charge trapping resulting from a significant reduction in film volume as well as kinetically suppressed crystallization. Metal thickness is also critical when optimizing physical stress effects and minimizing dopant diffusion. A high temperature anneal after source and drain implantation in a conventional CMOSFET process reduces the interface state density and improves electron mobility.

The dielectric breakdown property of ultrathin 2.5 and 5.0 nm hafnium oxide (HfO 2 ) gate dielectric layers with metal nitride (TaN) gate electrodes for metal oxide semiconductor (MOS) structure has been investigated. Reliability studies were performed with constant voltage stressing to verify the processing condition effects (film thicknesses and post metal annealing temperatures) on times to breakdown. The leakage current characteristics are improved with post metal annealing temperatures (PMA) for both 2.5 and 5.0 nm HfO 2 physical thicknesses. However, it is more prominent (∼2 orders of magnitudes) for 2.5 nm HfO 2 film thickness. The values of oxide-trapped charge density and interface-state density are also improved for 2.5 nm HfO 2 film. The different stages of charge-trapping behaviors, i.e., stress-induced leakage current, soft and hard breakdown mechanisms have been detected. During constant voltage stress of the MOS capacitors, an increase in the time-dependent gate current is observed, followed by the occurrence of several fluctuations. The amplitude of the fluctuations is much larger in the 5.0 nm HfO 2 gate dielectric layer compared to the 2.5 nm HfO 2 layer. After the occurrence of such fluctuations, the current–voltage characteristics exhibited an increased in gate current compared to the fresh (unstressed) devices.

Ultrathin nMOSFET hafnium oxide (HfO/sub 2/) gate stacks with TiN metal gate and poly-Si gate electrodes are compared to study the impact of the gate electrode on long term threshold instability reliability for both dc and ac stress conditions. The poly-Si/high-/spl kappa/ interface exhibits more traps due to interfacial reaction than the TiN/high-/spl kappa/ interface, resulting in significantly worse dc V/sub th/ instability. However, the V/sub th/ instability difference between these two stacks decreases and eventually diminishes as ac stress frequency increases, which suggests the top interface plays a minor role in charge trapping at high operating frequency. In addition, ac stress induced interface states (Nit) can be effectively recovered, resulting in negligible G/sub m/ degradation.

We have investigated the growth mechanism of ALD-TiN film on different dielectrics and the resulting effective work function value. TiN nucleation rate and growth rate are found to be dependent on the dielectric films. TiN growth mechanism changed from 3-D type on SiO 2 to layer-by-layer type on HfO 2 . The minimum TiN thickness required for a complete surface coverage varies according to the growth mechanism. Capacitor (MOSCAP) characterization revealed that the effective work function of TiN is dependent not only on dielectric films but also on the TiN thickness. The behavior of work function and fixed charge correlated with the growth mechanism of TiN on dielectric films.

To develop low-loss tunable microwave circuits, based on the field dependence of dielectric permittivity, phase pure (Ba 0.5 , Sr 0.5 )TiO 3 doped with 1% W (BST) thin films 0.3-μm thick were deposited on single crystal MgO wafers by pulsed laser deposition. The BST films were characterized by X-ray θ-2θ scans and pole figure analysis, field emission scanning electron microscopy (FESEM), and cross-sectional transmission electron microscopy (TEM), coupled with selected-area electron diffraction (SAED). Although, the X-ray θ-2θ scan indicated an epitaxial nature of BST with an out-of-plane orientation of (100), the pole figure analysis confirmed the presence (4-6%) of (111)-oriented grains in a matrix of (100) textured grains. The columnar grains exhibited an in-plane (i.e., along the plane perpendicular to the growth direction) grain size that was thickness-dependent. The cross-sectional TEM, coupled with SAED in the thickness direction, corroborated the pole figure analysis. Additionally, from X-ray analysis, it was observed that the textured films were under in-plane tension. The deposited film was characterized at microwave frequencies (1-20 GHz) using interdigitated electrodes deposited on top of the film. The film was characterized by a relatively low dielectric Q of 5-7. A 17% change in the capacitance was observed when applying a 40V bias. From the observed microstructure, a preliminary understanding of its evolution and its relationship with the microwave dielectric properties is discussed, and some ideas to obtain truly epitaxial BST films are presented.

Hole mobility and flicker noise characteristics of uniaxially strained ( 110)/〈110〉 Si0.75 Ge0.25 pFINFETs (SSGOI0.25) are investigated in this letter. Equivalent gate referred flicker noise in SSGOI0.25 is dominated by correlated number and mobility fluctuation in the low-bias regime and Hooge mobility fluctuation in the high-bias regime. The extracted Hooge parameter in SSGOI0.25 and in Si pFINFETs is 10-5 and 10-4, respectively. The lower value of the Hooge parameter in SSGOI0.25 pFINFETs is attributed to improved phonon-limited mobility compared to the SOI pFINFETs. SSGOI0.25 FINFETs are found to exhibit the lowest equivalent gate referred flicker noise among any nonplanar devices reported to date.

Double-gate FinFET (110) (110) and (100) (100} electron mobility (μe) and hole mobility (μh) are experimentally investigated for the following: 1) a wide range of boron and phosphorus fin doping concentrations and 2) a wide variety of gate stacks combining HfO2, SiO2, or SiON insulators with TiN or poly-Si electrodes. It is found out that, irrespective of fin doping and gate stack, (110) (110) μe is competitive with the (100)(100) μe, while (110)(110) μh is ≥ 2× higher than (100) (100) μh. Inversion μe and μh are independent of doping as long as the effective field/doping combination enables the screening of the depletion charge. Mobility degradation with doping is significantly lower in accumulation mode (AM) than in inversion mode (IM) such that, for heavily B-doped fins, AM hole mobility exceeds the IM electron mobility even in (100) FinFETs. In undoped fins, ALD TiN gate stress is observed to improve μe for both orientations without degrading μh.

A preliminary evaluation of Pt films, deposited at rates of 0.4-7 nm/min by a potentially manufacturable liquid-source MOCVD technique, was carried out with respect to microstructure, step coverage, and electrical properties. The Pt films (12-140 nm) were deposited on various substrates (thermal-SiO 2 /Si, native-oxide/Si, TiN/SiO 2 /Si) via the pyrolysis of trimethyl methyl cyclopentadienyl platinum [(CH 3 ) 3 CH 3 CpPt]. The substrate temperature regimes through which Pt deposition occurred, were 175-250°C and 300-450°C in H 2 and O 2 ambient, respectively. The growth mechanisms of the Pt films, deposited under H 2 and O 2 ambient, were inferred from the observed growth rate, texture evolution, grain size, and estimated nucleation density. Additionally, the step-coverage of Pt deposited on TiN at T sub of 375°C in O 2 was 80%. Moreover, the resistivity of a 30 nm Pt film was 22.8 w z -cm.

Recent experiments have demonstrated the ability to alleviate Fermi-level pinning, resulting in reduced Schottky barrier heights (SBHs) and reduced contact resistivity by inserting thin layers of dielectric at the contact interface. In this letter, FinFETs with dielectric SBH tuning layers are investigated and shown to have reduced contact resistance over the control wafer. The reduced contact resistivity results in an ≈25% increase in drive current as well as a reduction of RS/D by 100 Ω · μm. Contact chain measurement shows a 10-Ω · μm2 reduction in specific contact resistivity over the control wafer associated with a 100-meV reduction in SBH. Routes to further improvements in device performance are discussed, including key material considerations for dielectric tuning layers.

Highly (111)-oriented and conformal iridium (Ir) films were deposited by a liquid source metalorganic-chemical-vapor-deposition process on various substrates. An oxygen-assisted pyrolysis of (methylcyclopentadienyl) (1,5-cyclooctadiene) Ir precursor at a wide range of substrate temperatures (Tsub) between 300 and 700 °C was used. At a low Tsub of 350 °C, the randomly oriented polycrystalline films exhibited an I111/I200 x-ray intensity ratio of 6. However, the films deposited at Tsub = 700 °C on native SiO2 and amorphous SiO2 surfaces were highly oriented with the I111/I200 ratios of 277 and 186, respectively. The transmission electron microscopy study revealed continuous, dense, and faceted microstructures of Ir films. Also, the step coverage of Ir on TiN (64%) was higher than that on amorphous SiO2 (50%) surfaces.

The volatility of bismuth (Bi) presents difficulty in the integration of ferroelectric strontium bismuth tantalate (SrBi2Ta2O9 or SBT) thin films for FeRAM applications. This paper presents preliminary results indicating that the Bi volatility problem may be controlled by the addition of vanadium (V) to SBT. A series of V-doped SBT films (∼150 nm), of a nominal composition SrBi2.2(Ta1-xVx)2O9 with x = 0, 0.01, and 0.07, were deposited on Pt/SiO2/Si wafers by sol-gel processing. XRD and SEM revealed a polycrystalline morphology and a vanadium solubility in SBT of at least 7%. SBT with 7% V-doping exhibited little structural damage from a forming gas anneal. 7% V-doping also limited Bi diffusion into Pt bottom electrodes and increased the surface Bi 4f7/2 electron binding energies. The ferroelectric and polarization fatigue properties did not improve with V-doping, which was attributed to oxygen vacancy formation due to acceptor doping. Vanadium stabilized Bi in the SBT matrix by reducing from the ...

A novel, simple and economical chemical bath method for deposition of calcium hydroxyapatite coating has been developed. The coatings were prepared from EDTA solutions in alkaline media on Ti6Al4V substrates. The method is based on thermal dissociation of the Ca(EDTA)2- complex at 65–95 °C. Two chemical baths with and without presence of Na+ and Cl- were used for the deposition. The Rutherford back scattering study shows that the coating material from bath which contained sodium and chlorine ions have their presence in the coated material. The bath which has been prepared with potassium substituting sodium and nitrate substituting chlorine produced coatings with better stoichiometry, with Ca/P=1,67. The X-ray analysis revealed that the calcium hydroxyapatite coatings have preferred crystal orientation in the 002 direction. © 2001 Kluwer Academic Publishers