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Complementary metal–oxide–semiconductor (CMOS) technology is facing increasingly difficult obstacles such as power consumption and interconnection delay. Novel hybrid technologies and architectures are being investigated with the aim to circumvent some of these limits. In particular, hybrid CMOS/magnetic technology based on magnetic tunnel junctions (MTJs) is considered as a very promising approach thanks to the full compatibility of MTJs with CMOS technology. By tightly merging the conventional electronics with magnetism, both logic and memory functions can be implemented in the same device. As a result, non-volatility is directly brought into logic circuits, yielding significant improvement of device performances and new functionalities as well. We have conceived an innovative methodology to construct non-volatile magnetic arithmetic logic units (MALUs) combining spin-transfer torque MTJs with MOS transistors. The present 4-bit MALU utilizes 4 MTJ pairs to store its operation code (opcode). Its operations and performances have been confirmed and evaluated through electrical simulations. [ABSTRACT FROM AUTHOR]

Spintronics is a new discipline in which the spin of the electron is used as an additional degree of freedom besides its electrical charge to build innovative electronic components. Magnetic materials can be used as spin polarizer/analyzer in association with semiconductors or insulators, resulting in hybrid CMOS/magnetic architectures. Magnetic Tunnel Junctions (MTJ) are the basic elements of a new kind of memory, called MRAM (Magnetic Random Access Memory). Besides MRAM, it has recently been shown that by combining MTJ and CMOS components, one can also develop new functionalities for logic devices. This paper aims at giving a general overview of these novel hybrid magnetic/CMOS architectures and the design tools required for their design. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents a digital approach to frequency testing of Analogue and mixed-signal (AMS) circuits. This approach is aimed at facilitating low-cost test techniques for system-on-chip (SoC) devices, rendering the test of mixed-signal cores compatible with the use of a low-cost digital tester. Analogue test signal generation is performed on-chip by low pass filtering a sigma–delta (ΣΔ) encoded bit-stream. Analogue harmonic test response analysis is also performed on-chip using square wave modulation and ΣΔ modulation. Since both analogue signal generation and test response analysis are digitally programmable on-chip, compatibility with a low-cost digital tester is ensured. Optimisation of test signatures is discussed in detail as a trade-off between fault and yield coverage. A 0.18μm CMOS implementation of this BIST technique is presented, including some experimental results. [Copyright &y& Elsevier]

For embedded systems in harsh environments, a radiation robust circuit design is still an open challenge. As complementary–metal–oxide semiconductor (CMOS) processes get denser and smaller, their immunity toward particle strikes decreases drastically. Due to its good radiation effects tolerance and its inherent nonvolatility, spin-transfer torque magnetic tunnel junction (STT-MTJ) is considered a promising candidate for high-reliability electronics. Nevertheless, when integrated in a CMOS circuit, these magnetic devices could still be affected by upsets. To decrease the probability of this occurrence, a radiation robust setup is used to calibrate a physics-based 20-nm MTJ compact model, integrated in a 28-nm Fully Depleted Silicon On Insulator (FD-SOI) technology. Thus, a radiation hardening by design (RHBD) solution is presented, where a nonvolatile sequential block enables one to mitigate the single-event effects (SEEs). [ABSTRACT FROM AUTHOR]

High endurance, high speed, scalability, low voltage, and CMOS-compatibility are the ideal attributes of memories that any integrated circuit designer dreams about. Adding non-volatility to all these features makes the magnetic tunnel junctions (MTJs) an ultimate candidate to efficiently build a hybrid MTJ/CMOS technology. Two-terminal MTJs based on spin-transfer torque (STT) switching have been intensively investigated in literature with a variety of model proposals. Despite the attractive potential of the STT devices, the issue of the common writing/reading path decreases their reliability dramatically. A three-terminal MTJ based on the spin-orbit torque (SOT) approach represents a pioneering way to triumph over current two-terminal MTJs by separating the reading and the writing paths. In this paper, we introduce the first compact model, which describes the SOT-MTJ device based on recently fabricated samples. The model has been developed in Verilog-A language, implemented on Cadence Virtuoso platform and validated with Spectre simulator. For optimized simulation accuracy, many experimental parameters are included in this model. Simulations prove the capability of the model to be efficiently used to design hybrid MTJ/CMOS circuits. Innovative logic circuits based on the SOT-MTJ device, modeled in this paper, are already in progress. [ABSTRACT FROM PUBLISHER]

Magnetic tunnel junctions (MTJ) are considered as one of the most promising candidates for the next generation of nonvolatile memories and programmable logic chips. Spin transfer torque (STT) in CoFeB/MgO/CoFeB MTJs with perpendicular magnetic anisotropy (PMA) exhibits noticeable performance enhancements compared to that with In-plane magnetic anisotropy, particularly in terms of thermal stability, critical current for switching, access speed and power consumption. However, the STT switching of MTJ has been revealed stochastic, which results from unavoidable thermal fluctuations of magnetization. This leads to the occurrence of write errors which deeply affects the reliability of hybrid CMOS/MTJ circuits. In this paper, we present the first spice-compact model of CoFeB/MgO/CoFeB structure PMA-MTJ integrating STT stochastic behaviors. Depending on the relative magnitude between the switching current (I) and the critical current (Ico), the STT stochastic behaviors of this PMA-MTJ can be categorized into two regions: Sun model (I>Ico) and Neel-Brown model (I<0.8Ico). The Monte-Carlo simulations for single cell and hybrid CMOS/MTJ circuits show the stochastic behaviors in both writing and sensing operations. This model can be very useful for investigating the reliability issues during the design and simulation before process fabrication. [ABSTRACT FROM AUTHOR]

• Scaling and controlling the synaptic current is indispensable for integrating emerging non-volatile memories (eNVMs) into different grids and design choices of advanced CMOS Technology nodes. • The maximum current scaling down factor depends on the leakage current of the spiking neuron, and the saturation conditions of the current source of the transconductance amplifier. • The fan-in of the 28 nm FD-SOI analog spiking neuron depends on the eNVMs technology, the width and amplitude of input spikes, the firing threshold of the neuron, and the current scaling down factor. • The tunable and versatile current attenuator allows the integration of various eNVMs into 28 nm FD-SOI technology based analog spiking neural networks. In this work we report a study and a co-design methodology of an analog SNN crossbar output circuit designed in a 28 nm FD-SOI technology node that comprises a tunable current attenuator and a leak-integrate and fire neurons that would enable the integration of emerging non-volatile memories (eNVMs) for synaptic arrays based on various technologies including phase change (PCRAM), oxide-based (OxRAM), spin transfer and spin orbit torque magnetic memories (STT, SOT-MRAM). Circuit SPICE simulation results and eNVM experimental data are used to showcase and estimate the neurons fan-in for each type of eNVM considering the technology constraints and design trade-offs that set its limits such as membrane capacitance, supply voltage, leakage, etc. [ABSTRACT FROM AUTHOR]

This letter presents magnetic tunnel junction based spintronic devices completely implemented in a hybrid semiconductor process that comprises a complementary metal oxide semiconductor and a magnetic tunnel junction technology. To demonstrate the coexistence of both complementary metal oxide semiconductor circuits and magnetic tunnel junction based spintronic devices, a proof‐of‐concept circuit prototype comprising 40 spintronic devices and a digital complementary metal oxide semiconductor serial peripheral interface is fabricated. According to measurement results, a selected spintronic device from the magnetic tunnel junction array, when surrounded by an external out‐of‐plane magnetic field of 1 kOe, emitted microwave signals from 2.235 to 2.464 GHz with an output power from 0.88 to 0.72 nW, when the DC current was increased from 0.6 to 1.0 mA. To the authors' best knowledge, this is the first work demonstrating the functionality of spintronic oscillators fully integrated in complementary metal oxide semiconductor circuit implemented in a hybrid complementary metal oxide semiconductor and magnetic tunnel junction process. [ABSTRACT FROM AUTHOR]

Perpendicular-anisotropy magnetic tunnel junction (MTJ) is one of the most promising candidates to build hybrid logic-in-memory architecture, because of its nonvolatility, infinite endurance, and 3-D integration with a CMOS technology. A novel magnetic full-adder (MFA) based on this architecture is proposed, with MTJs switched by spin-Hall-assisted spin-transfer torque (STT). Owing to the assistance of spin-Hall effect (SHE), MTJ switching time can significantly be reduced, and high operation frequency can be achieved. Moreover, the endurance of oxide barrier is largely enhanced as the requirement of lower write voltage. Using an industrial CMOS 28 nm design kit and a physics-based three-terminal spin-Hall-assisted STT-MTJ model, functionality and performance of the proposed MFA have been simulated and validated. A 1 ns STT current pulse assisted by 0.35 ns SHE current pulse is sufficient to switch the MTJ configuration. When compared with the previous MFAs based on STT-MTJ, the proposed MFA achieves 38% less operation time and 31% less power consumption to perform read and write operations. [ABSTRACT FROM AUTHOR]