1. Implementation of LVCMOS based 4 Bit FPGA Based ALU on SP 701 Board for New Digital Age Technologies
- Author
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Dr. Chandrashekhar Patel, Prof. Abhay Saxena, Prof. (Dr.) Anita Rawat, Prof. Omprakash Nautiyal, and Dr. Chandrashekhar Patel
- Subjects
SP701, FPGA, VIVADO, RISC, LVCMOS, Verilog - Abstract
Objectives: The 4-bit ALU of a RISC processor is designed as shown by the researcher in this paper. The 4-bit ALU used in this work can perform 2 4 = 16 various arithmetic and logical operations, including addition, subtraction, multiplication, and division as well as logical AND, OR, NAND, NOR, NOT, XOR, XNOR, INCREMENT, DECREMENT, ROTATE LEFT, and ROTATE RIGHT. Methods: The author used the Vivado simulation tools with the Verilog HDL language to build the FPGA-based ALU, and the SP701 Spartan FPGA board was used to implement the entire design. It has been implemented to use energy-efficient IO standard approaches. Findings: By calculating the overall power usage at the pre- and post-levels, this research has developed a new method for building energy-efficient FPGA-based ALUs. Author utilized Vivado simulation tool for this investigation. The SP701 FPGA board has also been used to implement this idea. Novelty: The Internet of Things and other emerging digital era technologies will undoubtedly benefit from this research work, and its energy efficient design will support environmental initiatives.
- Published
- 2023