Search

This paper presents an architecture and an optimization framework that uses partial response (PR) equalization for high-speed links. PR equalization is achieved through a combined use of linear transmit equalization and decision feedback equalization (DFE). This technique outperforms full-channel/impulse equalization for a wide range of channels in wireline communication. The constrained PR response equalization technique presented here improves eye openings, reduces the overall bit error rate, and reduces crosstalk impact for a large class of channels while maintaining a simple implementation. The new transceiver architecture proposed is particularly well suited for high-speed multichannel applications due to the mitigated DFE loop timing constraint. In comparison with duobinary equalization, the proposed PR architecture improves the eye height and eye width of the receiver by 28% and 10%, respectively, at 10 Gb/s and by 19% and 7%, respectively, at 15 Gb/s. The performance improvements in comparison to impulse equalization are even larger. Index Terms--Bit error rate (BER), decision feedback equalization (DFE), minimum mean-squared error (MMSE), partial response (PR), pulse amplitude modulation (2-PAM).

This paper presents modulation strategies for cascaded multilevel inverters that substantially eliminate common-mode voltage on the output phases. The paper begins by developing generic multilevel inverter reference waveforms that use only 'allowed' space vectors to achieve reduced common-mode voltage. A graphical technique is then proposed that allows various carrier disposition modulation strategies for a diode-clamped inverter to be converted to equivalent modulation of a cascaded inverter for any fundamental reference waveform. This graphical technique is confirmed for both Alternative Phase Opposition Disposition and Phase Disposition equivalent modulation of a cascaded inverter, and is then used to create reduced common-mode modulation strategies for cascaded inverters from their equivalent counterparts for diode-clamped inverters under hath continuous and discontinuous switching conditions. The strategies have been confirmed by both simulation and experimental results obtained using a cascaded five-level inverter. Index Terms--Common-mode voltages, harmonic analysis, multilevel inverters, pulsewidth modulation (PWM).

Results of a comparative investigation of deterministic and random pulsewidth modulation (PWM) techniques to be employed in a new ac drive for electric vehicles are presented. The study, employing the advanced simulation package SABER from Avant! Corporation, was focused on the reduction of electromagnetic interference (EMI) when a deterministic PWM strategy is replaced with an RPWM method. To assess the impact of the PWM technique on the drive performance, the drive efficiency, torque ripple, and dynamic response of the current control system were also investigated. Two RPWM techniques characterized by random variations of switching frequency of the inverter were considered: one with the sampling frequency of the modulator varying in step with the switching frequency, and one with a fixed sampling frequency equal to the average switching frequency. The study has demonstrated good EMI-mitigating potentials of RPWM techniques, whose use results in EMI reduction by 10 dB and more, while the drive performance is barely affected. Index Terms--AC drives, electric cars, electromagnetic interference (EMI), inverter control, random pulsewidth modulation (RPWM).