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This paper presents a hardware-software co-design for efficient sparse deep neural networks (DNNs) implementation in a regular systolic array for real-time on-device speech processing. The weight pruning format, exploring pattern-based coordinate-assisted (PICA) sparsity, expands the pattern-based pruning into both convolutional neural networks (CNNs) and recurrent neural networks (RNNs). It reduces the index storage overhead as well as avoids accuracy degradation. The proposed systolic accelerator leverages the intrinsic data reuse and locality to accommodate the PICA-based sparsity without using complex data distribution networks. It also supports DNNs with different topologies. By reducing the model size by 16x, PICA sparsification reduces 6.02x index storage overhead while still achieving 20.7% WER in TIMIT dataset. For the pruned WaveNet and LSTM, the accelerator achieves 0.62 and 2.69 TOPS/W energy efficiency, 1.7x to 10x higher than the state-of-the-art.

Background Early detection of gait abnormalities is critical for preventing severe injuries in future falls. The timed up and go (TUG) test is a commonly used clinical gait screening test; however, the interpretation of its results is limited to the TUG total time. Research question What is diagnostic accuracy of the low-cost, markerless, automated gait analyzer, with the aid of vision-based artificial intelligence technology, which extract gait spatiotemporal features and screen for abnormal walking patterns through video recordings of the TUG test? Methods Our dataset contained retrospective data from outpatients from the Department of Neurology or Rehabilitation of two tertiary hospitals in Shanghai. A panel of three expert neurologists specialized in movement disorders reviewed the gait performance in each TUG video, and labeled them separately, with the most commonly assigned label being used as the reference standard. The gait analyzer performed the AlphaPose algorithm to track the human joint position and calculated the spatiotemporal parameters by filtering and double-threshold signal detection. Gait spatiotemporal features and expert labels were input into machine learning models, and the accuracy of each model was tested with leave-one-out cross-validation (LOOCV). Results A total of 284 participants were recruited. Among these, 100 were labeled as having abnormal gait performance by experts. The Naive Bayes classifier achieved the best performance with a full-data accuracy of 90.14% and a LOOCV accuracy of 89.08% for screening abnormal gait performance. Significance This study is the first to investigate the accuracy of a vision-based intelligent gait analyzer for screening abnormal clinical gait performance. By virtue of a pose estimation algorithm and machine learning models, our intelligent gait analyzer can detect abnormal walking patterns approximate to judgements made by experienced neurologists, which is expected to be a supplementary gait assessment protocol for basic-level doctors in the future.

Intensive information is emerged in social media every second. Many breaking news often appear first in social media, much earlier than they appear in traditional news media. Through the technology of event detection on social media data streams, scatter information can be gathered together to inform us the popular events discussing online. An event is often modeled as a cluster of documents which discuss the same subject. Traditional event detection methods perform poorly on social media because of their huge amount of data and irregular expressions. In this paper, we propose a simple yet efficient event detection method towards social media. An event is represented by a sequence of keywords extracted from social media. We use a single-pass incremental clustering method with a trained encoder mapping documents and events into the same semantic space, which is helpful for the similarity calculation between them. We consider the similarity calculation between a tweet and an event as a matching process and construct a relevance matching dataset with tweet-event pairs. We finetune BERT (Bidirectional Encoder Representations from Transformers) model in the matching dataset to get an appropriate semantic encoder. Keywords are dynamically changed to represent an event for capturing the development of the event. Our proposed method achieves 0.86 on NMI (Normed Mutual Information), 0.69 on ARI (Adjusted Rand Index) and 0.70 on F1-score on a public twitter dataset, which shows the superiority of our method compared with baseline methods.

Dementia refers to a group of syndromes with cognitive impairment as the main clinical manifestation. Amongst various neuropsychological tests for clinical diagnosis of dementia, the clock drawing test (CDT) is frequently used due to its simplicity and effectiveness. In order to extricate physicians from their involvement in CDT scoring, we propose an automatic scoring method via object detection for accurate and efficient dementia screening. Given the drawn clock picture by a testee, this end-to-end method for CDT scoring directly produces the final score without any human interventions. Moreover, the proposed method can handle two ways of data acquisition scanned data set which contains the scanned version of drawn clocks and camera data set which consists of the drawn clocks taken from normal cameras. Extensive experimental results demonstrate the validity and feasibility of the proposed method. Specifically, the precision of the scanned dataset scored by a seven-point method and the camera dataset by a three-point method is 94.64% and 92.36% respectively, while that of junior outpatient physicians is 92.03% within the camera dataset.

Facial expression recognition (FER) plays a crucial role in human-computer interaction and is a challenging task due to the drastic face appearance variations across head poses. In order to classify different expressions under arbitrary poses, in this paper, we utilize an end-to-end encoder-decoder network by leveraging both 2D and 3D modalities for simultaneous facial expression recognition and 3D Morphable Model (3DMM) expression part reconstruction. Specifically, an encoder regresses expression representations from 2D images, and a decoder recovers 3DMM expression parts from corresponding expression representations. These two components are trained jointly with an expression classification loss being explicitly enforced over expression representations. For handling lack of non-frontal views in FER databases, we also generate the profile views of face image with out-of-plane rotation. Finally, the learned expression representations are desirably discriminative, generative and robust to pose variations. Within extended CK+ and Oulu-CASIA database, our proposed method outperforms ExpNet by 34.20% and 30.56% respectively, demonstrating the superiority of the proposed method.

Three-dimensional (3-D) integration, a breakthrough technology to achieve “More Moore and More Than Moore,” provides numerous benefits, e.g., higher performance, lower power consumption, and higher bandwidth, by utilizing vertical interconnects and die/wafer stacking. This paper presents an overview of 3-D integration along with various design challenges and recent innovations. — Partha Pande, Washington State University

Processing-in-memory (PIM) provides high bandwidth, massive parallelism, and high energy efficiency by implementing computations in main memory, therefore eliminating the overhead of data movement between CPU and memory. While most of the recent work focused on PIM in DRAM memory with 3D die-stacking technology, we propose to leverage the unique features of emerging non-volatile memory (NVM), such as resistance-based storage and current sensing, to enable efficient PIM design in NVM. We propose Pinatubo1, a Processing In Non-volatile memory ArchiTecture for bUlk Bitwise Operations. Instead of integrating complex logic inside the cost-sensitive memory, Pinatubo redesigns the read circuitry so that it can compute the bitwise logic of two or more memory rows very efficiently, and support one-step multi-row operations. The experimental results on data intensive graph processing and database applications show that Pinatubo achieves a ∼500 x speedup, ∼28000x energy saving on bitwise operations, and 1.12× overall speedup, 1.11× overall energy saving over the conventional processor.

The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, is one of the promising solutions to mitigate the interconnect problem in modern microprocessor designs. To leverage the benefits of fast latency, high bandwidth, and heterogeneous integration capability that are offered by 3D technology, new design methodologies should be developed targeting the unique feature of 3D integration. In this chapter, various approaches to model 3D electrical behavior, handle 3D thermal reliability problems, and design future 3D microprocessors are surveyed.

Energy becomes the primary concern in nowadays multi-core architecture designs. Moore's law predicts that the exponentially increasing number of cores can be packed into a single chip every two years, however, the increasing power density is the obstacle to continuous performance gains. Recent studies show that heterogeneous multi-core is a competitive promising solution to optimize performance per watt. In this paper, different types of heterogeneous architecture are discussed. For each type, current challenges and latest solutions are briefly introduced. Preliminary analyses are performed to illustrate the scalability of the heterogeneous system and the potential benefits towards future application requirements. Moreover, we demonstrate the advantages of leveraging three-dimensional (3D) integration on heterogeneous architectures. With 3D die stacking, disparate technologies can be integrated on the same chip, such as the CMOS logic and emerging non-volatile memory, enabling a new paradigm of architecture design.1

3D integration is an emerging interconnect technology that can enable the continuation of performance scaling and the reduction of form factors. There are various approaches for 3D integration, including system-in-package (SiP), TSV-based 3D ICs, monolithic 3D ICs, and inductance/capacitance coupling 3D ICs, among which TSV-based 3D IC is the most promising one. This paper provides a summary of previous work on electrical modelings for 3D IC, with an emphasis on two key interconnect approaches: TSVs and RDLs. Based on prior work, we describe a compact model standard to facilitate a generic modeling approach for future 3D ICs.

Electromigration (EM) can cause severe reliability issues in contemporary integrated circuits. For the emerging three-dimensional integrated circuits (3D ICs), the introduction of through-silicon vias (TSVs) as the vertical signal carrier complicates the electromigration analysis. In particular, an accurate EM analysis on TSV arrays that are used in the power supply network is critical since the large current going through those TSVs can accelerate their degradation. In this work, we propose a novel EM analysis framework that focuses on TSV arrays in the power supply network, under the circumstance of uneven current distribution. The impacts of various design factors on the EM lifetime are discussed in detail. Our results reveal that the predicted TSV array lifetime is largely biased without proper current distribution analysis, resulting in an unexpected early failure.

3D integration is one of the promising solutions to overcome the interconnect bottleneck with vertical interconnect through-silicon vias (TSVs). This paper investigates the crosstalk in 3D IC designs, especially the capacitive crosstalk in TSV interconnects. We propose a novel ω-LAT coding scheme to reduce the capacitive crosstalk and minimize the power consumption overhead in the TSV array. Combining with the Transition Signaling, the LAT coding scheme restricts the number of transitions in every transmission cycle to minimize the crosstalk and power consumption. Compared to other 3D crosstalk minimization coding schemes, the proposed coding can provide the same delay reduction with more affordable overhead. The performance and power analysis show that when ω is 4, the proposed LAT coding scheme can achieve 38% interconnect crosstalk delay reduction compared to the data transmission without coding. By reducing the value of ω, further reduction can be achieved1.

Phase change memory (PCM) has been widely studied as a potential DRAM alternative. The multi-level cell (MLC) can further increase the memory density and reduce the fabrication cost by storing multiple bits in a single cell. Nevertheless, large write power, high write latency, as well as reliability issue resulted from the resistance drift, bring in challenges for MLC PCM based memory design. In contrast, the emerging Resistive Random Access Memory (ReRAM), which has similar MLC property as PCM, demonstrates better performance and energy efficiency compared to PCM. In addition, due to the physical switching behaviors of ReRAM cell, the resistance drift phenomenon does not exist. In this paper, we propose a low power MLC ReRAM design. We first study the programming method of MLC ReRAM and identify that programming latency and energy are highly dependent on the data pattern written to the cell. Based on this observation, we propose incomplete data mapping (IDM), which maps an eight-level-cell into six states to prevent the time/energy consuming data patterns from appearing in the cell. Furthermore, in order to improve endurance of MLC RAM, which is much smaller than single-level cell (SLC) ReRM due to the complex programming method, we propose Dynamic Data ReMapping (DDRM) to selectively regulate memory blocks from IDM state back to complete data mapping (CDM) state. We demonstrate that the proposed design can work effectively with existing error-correction schemes but requires much smaller space overhead. Experimental results show that, IDM can reduce the energy performance by at most 15% with negligible performance overhead. By combining the DDRM with existing error-correction scheme, DDRM can improve the memory lifetime by 2.75× compared with conventional memory architectures.

Three-dimensional integrated circuit (3D IC) is a promising solution to continue the performance scaling. However, the fabrication cost for 3D ICs can be a major concern for the adoption of this emerging technology. In this paper, we study the cost implication for both TSV-based and interposer-based 3D ICs, with the observation that many long metal interconnects in 2D designs are replaced by TSVs in 3D designs, and therefore the number of metal layers to satisfy routing requirements can be reduced, resulting in cost saving in 3D ICs. Based on our cost model, we propose a cost-driven 3D design space optimization flow that balances the design area and metal layer requirement, by optimizing the cost tradeoffs between silicon area and the number of metal layers. With the cost-driven design optimization flow, we can achieve cost saving up to 19% for TSV-based 3D designs, and 26% for interposer-based 3D designs, respectively, compared to the baseline designs.

Three-dimensional (3D) ICs promise to overcome barriers in integration density and interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved performance, higher memory bandwidth, smaller form factors, and heterogeneous integration. 3D integration provides additional architectural and technology-related design options for future system-on-chip (SoC) designs, making the early design space exploration more critical. This paper proposes a system-level design partition and hardware/software co-synthesis framework for 3D SoC integration. The proposed methodology can be used to explore the enlarged design space and to find out the optimal design choices for given design constraints including form factor, performance, power, or yield.