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A recently proposed technique for the distributed modeling of extrinsic parasitic effects in electron devices is used for the very first time in conjunction with a lumped equivalent circuit model for the intrinsic device.Nonlinear modeling of 0.1 μm InP HEMTs for W-band applications is considered here, leading to extremely accurate predictions of harmonic distortion and power added efficiency at the fundamental frequencies of 27 and 94 GHz.The distributed parasitic network is identified through accurate electromagnetic simulations up to the upper frequency limit of the millimeter-wave band (300 GHz), while standard pulsed I/V and S-parameter measurements up to 67 GHz are used for the identification of the intrinsic device model.

Electron device modeling requires accurate descriptions of parasitic passive structures connecting the intrinsic electron device to the external world. In conventional approaches, the parasitic phenomena are described by a network of lumped elements. As an alternative, a distributed description can be conveniently adopted. This choice has been proven very appropriate when dealing with device scaling and very high operating frequencies. In this paper, a novel approach to distributed parasitic modeling is adopted for the very first time in association with a nonlinear electron device model. In particular, it is shown how an equivalent intrinsic device and a suitably defined distributed parasitic network can be accurately defined and modeled on the basis of standard measurements and easy electromagnetic simulations. Wide experimental validation based on GaAs pseudomorphic HEMTs is provided, showing accurate prediction capabilities both under small- and large-signal conditions. The proposed model is shown to perform optimally even after periphery scaling.

A double-pulse technique for the I/V characterization of GaN-based transistors is adopted for the nonlinear modeling of a 0.25 μm AlGaN/GaN on SiC FET. Experimental validation is provided by means of large-signal PA performance prediction both at low-frequency, in order to outline the role played by the resistive drain current source, and at microwaves. Improved prediction accuracy is demonstrated with respect to the use of standard single-pulse I/V characteristics.

A new modeling approach has been developed for the accurate prediction of the dynamic drain current of GaN FETs. This is accomplished by separation of the low (LF) and high (HF) frequency transistor dynamic behavior.

Cascode field-effect transistors (FETs) are widely used in the design of monolithic microwave integrated circuits (MMICs), owing to their almost unilateral and broadband behavior. However, since a dedicated model of the cell is rarely provided by foundries, a suboptimal description built by replicating the standard foundry model for both the common source and common gate device is often adopted. This might limit the success of the MMIC design at the first foundry run. This paper describes an electromagnetic-based empirical model of cascode cells, covering topics from the formulation and identification procedures to the corresponding validation described in an exhaustive experimental section. A MMIC low-noise distributed amplifier case is then presented and the proposed model is used for circuit analysis and instability detection. Clear indication is provided about the improvement in the prediction of critical behaviors with respect to conventional modeling approaches. A cascode cell with a symmetric layout is also successfully modeled.

A new method is proposed for the empirical characterization of the nonlinear thermal resistance in GaN HEMTs. Low-Frequency dispersion due to self-heating is used as the sensing parameter of the channel temperature changes deriving from dissipated power variations. Since GaN HEMTs are also affected by LF dispersive charge-trapping phenomena, the thermal resistance description is embedded into a full electrothermal model, in order to extract the parameters by bestfitting the measured data. The method involves only multi-bias small-signal S-parameter and dc I/V measurements at different base plate temperatures. It is non-invasive, does neither require special-purpose device geometries/structures nor measurements in the conduction region of the gate junction. Preliminary validation of the method is based on comparisons with measured electrothermal data, with data from the literature on similar devices and on results provided by a large-signal RF device model embedding the thermal resistance description.

A large-signal measurement setup with sinusoidal excitation is used for the characterization of low-frequency dispersive phenomena in III-V FET devices. This low-cost setup operates in the MHz frequency range and its components are easily available in most research laboratories. A dispersive model of the dynamic drain current, taking into account the non linear behaviour of charge trapping phenomena, is identified for an AlGaN/GaN HEMT on the basis of the proposed characterization setup.

Cascode FETs are widely used in the design of MMICs, owing to their almost unilateral behavior. An accurate model of the cell is indeed necessary in order to achieve good circuit performance estimations. In the literature, the Cascode cell models are usually obtained on the basis of measurements of the entire structure or by a preliminary characterization of the common source elementary cell. However, the different influence of the parasitic network between common source and common gate topologies are not taken into account in the latter case. In this paper, a distributed approach based on EM simulations is adopted for the modeling of the parasitic network of the Cascode cell. The proposed procedure leads to a well conditioned characterization of the intrinsic devices, which can be used for the modeling of both the common source and the common gate transistors. Wide experimental validation is provided in the paper.

Le antenne integrate attive (AIA), rappresentano la nuova frontiera nella progettazione dei moderni sistemi a radiofrequenza e ad onde millimetriche, sia per applicazioni militari che per applicazioni commerciali. Negli ultimi anni, la progettazione dell’antenna, oltre al raggiungimento dei requisiti sul diagramma di irradiazione, sul guadagno e sull’adattamento di impedenza, richiede una forte integrazione dell’elemento radiante nel sistema. Infatti, nei sistemi di trasmissione, ed in special modo in quelli mobili, è di fondamentale importanza ridurre al minimo la dissipazione di potenza in continua, per aumentare la durata delle batterie e per ridurre il peso e l’ingombro dell’intera unità, riducendo sia le dimensioni dei sistemi di alimentazione che dei sistemi di raffreddamento. Fattori cruciali nelle scelte progettuali saranno quindi l’efficienza, le dimensioni e la larghezza di banda, oltre al controllo delle interferenze elettromagnetiche tra i vari sottosistemi. Allo scopo di investigare questi nuovi concetti e sviluppare strutture innovative, è stato proposto e finanziato il progetto PRIN’05 dal titolo “Antenne Integrate Attive per Terminali Mobili ad Alta Efficienza”. Il progetto di ricerca si pone come obiettivo lo sviluppo di un’antenna integrata attiva per terminali mobili ad alta efficienza per applicazioni in banda Ku. Gli aspetti innovativi proposti riguardano la possibilità di integrazione dell’elettronica di front-end con l’elemento radiante, al fine di migliorare le prestazioni dell’intero trasmettitore. Le problematiche di rilievo sono l’integrazione dello stadio di potenza con il singolo elemento radiante, lo sviluppo di oscillatori VCO basati su1 concetto di injection locking per l’implementazione di array fasati e lo studio delle problematiche di sviluppo di array ad alta efficienza. Per quanto riguarda lo stadio di potenza integrato con l’elemento radiante, l’idea è stata quella di usare quest’ultimo anche come carico armonico per l’ottimizzazione delle prestazioni dello stadio di potenza.

This paper describes the design of a GaAs monolithic high power amplifier at Ku band. The chip delivers about 40 dBm of saturated output power, in CW operating conditions, at 11.7 GHz central frequency, with 17% of bandwidth. The saturated power gain is 12.4 dB with 2 dB gain flatness across the application bandwidth while the chip power added efficiency is estimated between 33% to 47%. The amplifier is designed to be used as final stage of a downlink satellite transmitter for Tracking Telemetry & Command system. A commercial power p-HEMT process capable of handling a power density higher than 1 W/mm has been selected for the MMIC design. Due to the space application, special attention must be put on the process and MMIC reliability: to this aim performances must be guaranteed in de-rated conditions respect to the process maximum ratings and, in addition, the channel temperature of the active devices must be kept within the value established by Space Requirements and carefully controlled. This makes the design objective very tight. The MMIC power amplifier design and some measurement results are presented in the paper.

In this contribution an innovative Active Integrate Antenna (AIA) system is presented. Starting from a critical revision of the state-of-the-art, alternative and innovative solutions to obtain a high degree of integration have been considered.

Electron device modelling requires the accurate identification of a suitable parasitic network accounting for the passive structures which connects the intrinsic electron device to the external world. In conventional approaches, the parasitic network is described by a proper topology of lumped elements. As an alternative, a distributed description of the parasitic network can be conveniently adopted. This choice finds out to be a very good one when dealing with device scaling and very high operating frequencies. In this paper the parasitic network is described by means of a suitable distributed network identified through electromagnetic simulations of the device layout. Experimental results prove that such a distributed approach provides models, which linearly scale with the channel width and are capable of accurate predictions even under operation at much higher frequencies than the experimental characterisation range.

This paper describes the design and implementation of 2 hybrid high power amplifiers at L band for a space application. Indeed, the amplifiers represent prototype test vehicles for a larger hybrid amplifier to be used as the final power stage in the transmitting chain of a T/R module of an L-band SAR antenna for earth observation. The amplifiers described in this paper exploit a discrete bar of a commercial 0.35 mum pHEMT process as active device. The first amplifier, featuring a single discrete device, delivers 12 Watts with 56.5% PAE and 12.3 dB gain at 2 dB compression. The second amplifier exploits 4 discrete pHEMT bars using input/output microstrip splitter/combiner and lumped wire bonding/ceramic MIM capacitor output matching networks. It delivers 42 watts with 50% PAE and 13 dB gain at 2.5 dB compression. Since it is a space application, these performances have been achieved with the required de-rating on break-down voltages, current densities and operating channel temperature. The latter has been evaluated by means of a 3-D device model implemented in the framework of a finite differences numerical thermal simulator. In spite of the constraints due to space de-rating rules, the obtained output power densities are 1 W/mm and 0.875 W/mm for the single-discrete and the 4-discrete amplifiers, respectively, which represent a value very close to the state of the art for pHEMT processes.

Electron device modelling requires accurate descriptions of parasitic passive structures connecting the intrinsic electron device to the external world. In conventional approaches, the parasitic phenomena are described by a network of lumped elements. As an alternative, a distributed description can be conveniently adopted. This choice has been proved very appropriate when dealing with device scaling and very high operating frequencies. In this paper, a distributed parasitic network is adopted in association with a nonlinear electron device model. In particular, it is shown how an equivalent intrinsic device and a suitably-defined distributed parasitic network can be accurately defined and modelled on the basis of standard measurements and easy electromagnetic simulations. Wide experimental validation based on GaAs and InP PHEMTs will be provided, showing accurate prediction capabilities both under small- and large signal conditions. The proposed model is shown to perform optimally even after periphery scaling.

Electron device modelling requires the accurate identification of a suitable parasitic network accounting for the passive structures which connect the intrinsic electron device to the external world. In conventional approaches, the parasitic network is described by a proper topology of lumped elements. As an alternative, a distributed description of the parasitic network can be conveniently adopted. In particular, the latter solution is the better choice when dealing with device scaling and very high operating frequencies. In this paper the parasitic network is described by means of a suitable distributed network identified through electromagnetic simulations of the device layout. It is shown how the adoption of a distributed instead of a lumped description leads to a more accurate equivalent-circuit-based electron device model. The good scalability properties of the approach are also presented through experimental results.

Electron device modelling at very high frequencies needs, as a preliminary step, the identification of suitable parasitic elements mainly describing the passive structure used for accessing the intrinsic device. However, when dealing with device modelling at millimetre-wave frequencies conventional lumped parasitic networks necessarily become less adequate in describing inherently distributed parasitic phenomena. In this paper, a distributed approach is adopted for the modelling of the parasitic network and a new identification procedure, based on electromagnetic simulation and conventional S-parameter measurements, is proposed. The intrinsic device, obtained after de-embedding from the distributed parasitic network, is particularly suitable for the extraction of accurate nonlinear models. Preliminary validation results are provided in the paper.

This paper deals with the design of X-band T/R modules to be employed on a future generation Synthetic Aperture Radar (SAR) for space application. Since the final High Power Amplifier (HPA) stage of the transmitting chain directly affects the overall module performances (mainly efficiency and maximum output power), HPA topic has been deeply investigated. In particular, an HBT process has been extensively explored, because of its attractive features; however potential advantages can be really achieved only if thermal management is consistently addressed. In SAR applications the RF carrier phase control is of great concern and major causes of module output phase shifts have been identified: temperature variations of active devices, non-linear modulating phenomena (AM/PM conversion) and supply voltage dropping off. The designed HPA will successfully handle all of them without disregard efficiency. Expected improvements will be shown for the future generation T/R module employing the designed PA and future architecture solutions.

In this paper the design of a VCO using GaInP/GaAs HBT technology is presented. The VCO is designed to be a part of a PDH point to point radio system. To achieve low phase noise performances GaInP/GaAs HBT technology and push-push topology have been chosen. The MMIC includes predistorters to emphasize the second harmonic, f/sub 0//2 prescalers for PLL locking and buffer amplifiers. A fully monolithic microstrip resonator is coupled with integrated varactors to achieve the specified tuning bandwidth. Phase noise, bandwidth and power measurements will also be presented.

Nonlinear dynamic characterization of 1-mm GaN FETs is carried out by means of pulsed waveform excitations, applied through a recently proposed measurement setup. Due to fast trap capture phenomena, standard narrow-pulsed I/V characteristics are found to deviate from the ideal behavior. In this paper, the effects of the nonlinear charge trapping on pulsed I/V characteristics are experimentally observed thanks to a particular feature of the adopted measurement setup, which allows the monitoring of the DC drain current components of the pulses. In addition, the progressive degradation of the device performance due to charge trapping phenomena at increasing excitation amplitudes is shown by means of a new pulsing procedure. © 2013 European Microwave Association.

The paper introduces a new pulsed measurement system for the characterization of thermal and charge trapping effects in compound semiconductor III-V FETs. Minimization of reflections are obtained by pulse generation in a 50 Ω environment and separation between DC and AC path guarantees no variations of the average voltage values of pulses. Both GaAs- and GaN-based FETs are characterized and some differences between the two technologies are outlined as far as the charge trapping behaviour is concerned.