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The read or write operation on a core cell imposes a stress on the unselected core cells of that row, which is equivalent to that of a read operation. Such stress on the unselected core cell is termed as Read Equivalent Stress (RES). Considering RES principal, the power dissipation becomes very important constraint during fault testing of Static Random Access Memories (SRAMs) using March Tests. In order to minimise the power dissipation during testing of SRAMs, it has been found that the power consumption associated with RES is wholly unnecessary and is focused to be completely eliminated in our work. The novel RES Eliminating Pre-Charge Control Logic has been proposed to eliminate RES which exploits the fact that during test, the addressing sequence of SRAM is known well in advance. The proposed RES Eliminating Pre-Charge Control circuit ensures the complete elimination of RES as well as of power dissipation contributed by RES during test of SRAM. We have observed and analysed that the proposed R...

Developing nations are facing a huge gap in generation and demand of electricity across the world. In present scenario the demand of electricity is increasing day by day and the shortfall of electricity has become one of the major obstructions in the development of rural areas. There is a big gap between electricity supply and demand. In India it is very difficult that to give twenty four hours electric supply in rural areas. The traditional use of camel as draught animal, for the purpose of transport of goods and agricultural work, has been drastically reduced during last few decades, due to advancements and cheaper availability of mechanical machineries. In this research paper we experimentally studied the camel powered electricity generation system at National Research Centre on Camels (NRCC) Bikaner. Camel Energy in form of high torque low speed can be converted into low torque high speed through motion converting system i.e. gear and pulley mechanism for high RPM output. This high RPM (more than 3000) output is used for electricity generation. The electricity generated can be used directly or stored in the battery and later may be used whenever it is required either for DC light or AC light using inverter. According to experimental study a camel can comfortably generate electricity up to 1KW by rotating shaft. The complete set up for electricity generation using camel power has been designed, developed and physically commissioned at National Research Centre on Camels (NRCC) Bikaner.

Switching activity is much higher in test mode as compared to normal mode of operation which causes higher power dissipation, and this leads to several reliability issues. Output gating is proposed as a very effective low-power test technique, which is used to eliminate redundant switching activity in the combinational logic of circuit under test (CUT) during the shifting of test vectors in a scan chain. This method reduces the average power significantly, but it introduces performance overhead in normal mode of operation. In this work, a new output gating technique is proposed which eliminates redundant switching activity in combinational logic of CUT during shifting of test vectors without any negative impact on performance as compared to earlier proposed output gating techniques. The proposed design also improves the performance of the scan flop in functional mode with negligible area overhead incurred due to extra transistors. Experimental results show that our design has a more robust performance ove...

Performance enhancement has always been a primary design goal for designers. Modern automation technology demands for reliable low cost controllers, required for specific applications. The restricted resources limits the number of functional units available on a processor which results into lowered performance. The better performance can be achieved with splitting existing functional unit into smaller independent units. The split of arithmetic and logic unit into two independent units namely arithmetic unit and logic unit, provides the facility for simultaneous operation by both of the units. This results into lesser execution time. The simulator Simplescalar has been modified to simulate split ALU. The benchmarks are run in order to collect performance statistics. The simulation parameters, including execution time have been recorded for standard simulator having integral ALU unit, and for split ALU unit and further compared to show enhanced performance with split ALU.

This paper demonstrates the alternative measures to generate the Steep wave impulse by using Impulse Voltage Generator (IVG) for high voltage testing of porcelain insulators. The modification of IVG by incorporating compensation of resistor, inductor, and capacitor has been achieved and further performance of the modified system has been analyzed by applying the generated lightning impulse and analyzing the electrical characteristics of impulse waves under standard lightning and fast rise multiple lightning waveform to determine the effect to improve rise time. The advantageous results have been received and being reported such as increase in overshoot compensation, increase in capacitive and inductive load ranges. Such further reduces the duration of oscillations of standard impulse voltages. The reduction in oscillation duration of steep front impulse voltages may be utilized in up gradation of Impulse Voltage Generator System. Stray capacitance could further be added in order to get the minimized difference of measurement between simulation and the field establishment.

The improved safety margins in complex systems have attained prime importance in the modern scientific environment. The analysis and implementation of complex systems demands the well quantified accuracy and capability of measurements. Careful measurement with properly identified and quantified uncertainties could lead to the actual discovery which further may contribute for social developments. Unfortunately most scientists and students are passively taught to ignore the possibility of definition problems in the field of measurement and are often source of great arguments. Identifying this issue, ISO has initiated the standardisation of methodologies but its Guide to the Expression of Uncertainty in Measurement (GUM) has yet to be adapted seriously in tertiary education institutions for understanding the concept of uncertainty. The paper has been focused for understanding the concepts of measurement and uncertainty. Further a case study for calculation and quantification of UOM for high voltage electrical testing of ceramic insulators has been explained.

exponential increase in test cost is one of the new challenges being posed by technology scaling. This Paper has been aimed to deal with the issue of testing cost which adds to the chip cost. Here we propose a new pattern set for testing the arithmetic circuits which contains a minimum number of test vectors and easy to generate on the chip and hence supports at-speed testing of the circuit. Though maximum fault coverage is desired but practically generation of test vectors for testing of all the possible defects is not at all feasible. This leads to the modeling of defects as faults which facilitate for simplification of test generation process. Though various fault models have been proposed, the single stuck-at fault model is one of widely accepted model because of having closeness to the actual defects and also, it provide the algorithmic possibilities which, further helps in generation of test vectors. The desired smaller DPM (defective parts per million) levels for devices, creates the need for application of better fault models, which can model the defects in the most accurate fashion. This result in complex fault models which tends to make test generation tedious or even impossible and ultimately increase the test cost. Our motive is to cut down the test cost by finding the minimal number of test vectors for the test. If reduction in the patterns for one module is achieved, it would reduce the overall test cost. We propose universal pattern set which gives good fault coverage for arithmetic circuit with small set of vectors.

is a graphical record of the electrical tension of heart and has established as one the most important bio-signal used by cardiologists for diagnostic purposes and further to adopt an appropriate course of treatment. The difficulties faced in interpretation of ECG signals forced researchers to study about automatic detection of cardiac arrhythmia disorders. The data analysis techniques using specific computer software could easily interpret complex ECG signals, predict presence or absence of cardiac arrhythmia. This provides real time analysis and further facilitates for timely diagnosis. In this paper, Support Vector Machine (SVM) technique, using LibSVM3.1 has been applied to ECG dataset for arrhythmia classification in five categories. Out of these five categories, one is normal and four are arrhythmic beat categories. The dataset used in this study is 3003 arrhythmic beats out of which 2101 beats (70%) are used for training and remaining 902 beats (30%) have been used for testing purpose. Total performance accuracy is found to be around 95.21 % in this case.

In this paper, we propose a novel non-linear prediction based method for lossless video coding. This method exploits gradient energies to perform pixel by pixel prediction. A feedback mechanism based on prediction context is also proposed, which prevents the non-linear predictor from over adjusting its predicted value. To exploit the redundancies present in the residues, a context based residue coding scheme is devised. This scheme efficiently predicts sign and magnitude of the residue. Besides computational simplicity of the proposed method, experimental results show lower value of zero order entropy as compared to the competitive algorithms reported in the literature.

Soft error has become one of the major areas of attention with the device scaling and large scale integration. Lot of variants for superscalar architecture were proposed with focus on program re-execution, thread re-execution and instruction re-execution. In this paper we proposed a fault tolerant micro-architecture of pipelined RISC. The proposed architecture, Floating Resources Extended pipeline (FREP), re-executes the instructions using extended pipeline stages. The instructions are re-executed by hybrid architecture with a suitable combination of space and time redundancy.

Multiple copies of the same functional units are common in today's design. It allows us to reduce golden reference storage by performing comparison of output response of the identical circuits when identical input sequence is applied to them. We present output response comparison scheme for identical sequential circuits for delay test using static transition probability. This allows us to make selection independent of the input sequence.