Search

At IMAPS2021, we reported on 1-dimensional VCSEL arrays and the packaging technology developed for these arrays, but this time we present the manufacturing workflow and look at the challenges presented by the packaging of special long-wavelength 2-dimensional vertical-cavity surface-emitting laser (VCSEL) arrays in various dimensions. We will show that available packaging technologies for epoxy application by silk screening, die- and wire bonding can be adapted for the unique properties of the 2D VCSEL arrays, delivering high accuracy for production with great overall yield. Proof of the excellent reliability and lifetime will be given through mechanical and electro-optical testing results. The technologies developed for 2D laser arrays will enable new devices for various new applications like high channel count interconnects for data communication and high power VCSEL solutions for 3D sensing. The perfected wire bonding process secured a homogeneous monometallic structure of the wire bonds, a reduced, well defined bond loop height, with sufficient clearance of the bonding wire above the VCSEL surface. Properly set-up manufacturing procedures for the packaging of the VCSEL arrays are necessary to achieve high performance and reliability of the products presented. Processing of large 2D-VCSEL arrays will be part of the paper. 2D arrays have enabled VCSEL technologies to address a wide range of new laser-based sensing applications. VCSEL products vary from laser chips with only a few emitters for proximity sensors up to several thousands of emitters for LiDAR systems. Applications include systems for the automotive, industrial, medical and consumer markets. There is a strong and growing market opportunity for long wavelengths VCSELs, e.g. based on InP material enabling single mode and multi-mode 2D-VCSEL arrays from 1.3 to beyond 2 µm. For 3D sensing systems and free-space optical communication, long wavelength 2D-VCSEL arrays offer improved eye safety and further benefits. The long wavelength VCSELs discussed in this paper can be deployed in a wide range of sensing and optical communication applications.

In this paper we present an optimized manufacturing technique for special long-wavelength 1-dimensional and 2-dimensional Vertical Cavity Surface Emitting Laser Diode (VCSEL) arrays with focus on die bonding and a special wire bonding process as well as additional possibilities to make the manufacturing more productive and to increase the product quality, reliability, and life time. VCSEL arrays have a very broad application potential. Objective of this paper is the development of an assembly technology for long-wavelength VCSEL arrays with high positioning accuracy for automated production with high total yield, using gold-based conductive glue (because silver migration is a concern) securing high yield and extremely high reliability and lifetime. Due to special customer requirements, a final thickness of the conductive glue of 35 micron with low standard deviation is necessary. For highest reliability, gold wire bonding of the top side contact of the VCSEL to a silicon substrate with gold metallization has been a customer requirement. With the described technique we develop and produce customer specific products with dedicated wavelength, performance, and packaging options. Bases on our findings, very flexible and scalable solutions are possible, matching many different applications. Finally, we will present an overview of our results on the physical and electro-optical characterization of the VCSEL devices. This yielded a very productive manufacturing technique, meeting the requirements mentioned above. Special design features of the VCSEL ensure that the relatively high thermal resistance of the cured conductive glue layer does not impair the electro-optical properties or the lifetime of the VCSELs. For the interconnection of the top side contact we used gold wire with 20 microns diameter, using ball-wedge, Stand-Off Stich Bond process with special loop geometry, required by the customer. Due to the properties of the semiconductor material of the VCSELs a low bonding temperature is required, enabled by our special wire bonding process. Gold wire bonding delivered excellent results, by far exceeding the customer specification. The optical spectrum of the VCSELs and other measurements indicate that the assembly processes do not harm the laser diodes or their electro-optical properties. All customer requirements for the 1-dimensional and 2-dimensional VCSEL arrays have been met. The electro-optical and burn-in data furnished proof of the quality of the engineered assembly technology. The technologies developed for low current as well as high current laser arrays will enable new devices for a huge amount of new applications because of the novel manufacturing processes as well as innovative packaging of the VCSEL arrays.

We present a very compact hybrid detection module based on an advanced liquid-cooled low temperature cofired ceramic (LTCC) substrate. The double sided hybrid combines 144 photo detectors and four specialized flip chip readout ASICs (Application specific Integrated Circuits) used for the readout of scintillation crystals with application in time-of-flight positron emission tomography (PET) combined with magnetic resonance imaging (MRI). If MRI images and PET images are combined, completely new medical diagnostic and treatment prospects are feasible because the two techniques are complementary and they will offer both anatomical and functional information. One of the biggest challenges is the development of miniaturized detector modules that are highly functional and MRI compatible. Our SiPM (Silicon Photomultiplier) module has an area of 32.8 by 32.0 mm2 and contains 12 × 12 SiPMs in a pitch of 2.5 mm2. The SiPM readout of the 144 channels is performed by four PETA6 ASICs. The LTCC substrate with a 2.1 mm thickness has been manufactured using the most advanced technologies developed at Micro Systems Engineering GmbH To guarantee the manufacturability in serial or mass production, DP951 P2 green tape has been used. For the cooling channels, special technology has been developed by MSE. The liquid cooling channels inside the LTCC substrate provide excellent cooling for the ASICs, the SiPMs, and thermal insulation between ASICs and SiPMs and allow a very compact design of the detector modules, reducing their height by 50% compared with other technical solutions. We can insert a ring of our modules in an existing MR (Magnetic Resonance) scanner. Operating the SiPMs at low temperature improves their performance, reducing the effects of dark count rate and improving image quality. There is no heatsink, heat pipe, or other cooling element attached to the back side of the ASICs. To avoid interference between the PET and MRI system, short signal length is required for minimizing pickup loops and eddy currents. The 12 SiPM arrays with 2 × 6 geometry are wire bonded only at the edges of the SiPMs to the LTCC, enabling the use of nearly the whole detector area for photon detection, which is of paramount importance for excellent image quality. At the opposite side of the substrate, four ASICs with 272 μm bump pitch are flip chip solder assembled to the LTCC substrate including underfilling, and a few SMD (Surface Mount Device) components are mounted. A scintillator crystal array on top of the SiPMs converts gamma rays (511 keV photons produced from positron-electron annihilation) into light. We assume that the LTCC substrates and all components are fully MRI compatible, which is important for the integration of PET with MRI without mutual interference. The paper elucidates the impact of the used technology on the performance of advanced PET/MRI detector modules.

We present a very compact hybrid detection module based on an advanced liquid-cooled LTCC substrate. The double sided hybrid combines 144 photo detectors and 4 specialized flip-chip readout ASICs used for the readout of scintillation crystals with application in time-of-flight (TOF) Positron Emission Tomography (PET) combined with Magnetic Resonance Imaging (MRI). Positron Emission Tomography is mostly known for its use in oncology applications, cardiovascular disease, and imaging of brain functions. If MRI images and PET images are combined, completely new medical diagnostic and treatment prospects are feasible since MRI delivers precise anatomical information. One of the biggest challenges is the development of miniaturized detector modules that are highly functional and MRI compatible. Our SiPM module has an area of 32.8 by 32.0 mm2 and contains 12 × 12 SiPMs in a pitch of 2.5 mm2. The SiPM readout of the 144 channels is performed by four PETA6 ASICs. The LTCC substrate with 2.1 mm thickness has been manufactured using the most advanced technologies developed at MSE. In order to guarantee the manufacturability in serial or mass production, DP951 P2 green tape has been used. For the cooling channels, special technology has been developed by MSE. The liquid cooling channels inside the LTCC substrate provide excellent cooling for the ASICs, the SiPMs, and thermal insulation between ASICs and SiPMs and allow a very compact design of the detector modules, reducing their height by 50% compared with other technical solutions. This makes both smaller scanners and larger detector rings possible, the latter being needed for heavier patients. We can insert a ring of our modules in an existing MR scanner. Operating the SiPMs at low temperature improves their performance, reducing the effects of dark count rate and improving image quality. There is no heat sink, heat pipe, or other cooling element attached to the back side of the ASICs. In order to avoid interference between the PET and MRI system, short signal length is required for minimizing pickup loops and eddy currents. The 12 SiPM arrays with 2×6 geometry are wire bonded only at the edges of the SiPMs to the LTCC, enabling the use of nearly the whole detector area for photon detection, which is of paramount importance for excellent image quality. At the opposite side of the substrate, four ASICs with 272 μm bump pitch are flip-chip solder assembled to the LTCC substrate including underfilling, and a few SMD components are mounted. A scintillator crystal array on top of the SiPMs converts gamma-rays (511 keV photons produced from positron-electron annihilation) into light. LTCC substrates and all components are fully MRI compatible, which allows integration of PET with magnetic resonance imaging without mutual interference. The performance of a PET detector is characterized by its time resolution, energy resolution, detection efficiency, and spatial resolution. Each of these factors has a huge influence on the quality of the final PET image. All of these factors are improved with our novel technical solution. With measurements on prototypes, state-of-the-art coincidence time resolution (CTR) for pairs of identical detectors in combination with high spatial resolution have been obtained. The paper elucidates the impact of the employed technology on the performance of advanced PET/MRI detector modules. Novel features of the detector modules will help to enhance the “molecular sensitivity” of PET/MRI scanners.

Objective of this paper is the development of an assembly technology for VCSELs 360 micron by 360 micron in size and a thickness of 72 micron with high positioning accuracy for automated production. Due to special customer requirements, a final thickness of the conductive glue of about 50 micron is necessary. For highest reliability, gold wire bonding of the top side contact of the VCSEL to a silicon substrate with gold metallization and printing gold-based conductive glue have been used. One VCSEL array contains 512 diodes. Special design features of the VCSEL secure that the relatively high thermal resistance of the cured conductive glue layer does not impair the optical properties or the life time of the VCSELs. Die bonding has been carried out with a Datacon EVO machine. The singulated laser chips were picked from a blue tape. For the interconnection of the top side contact we used gold wire and a Stand-Off Stich Bond process with special loop geometry. With an optimized screen printing process we did get a reproducible height of the conductive glue of about 50 micron with low standard deviation, as required, and no shorts at the silicon substrate. The position tolerance of the VCSELs meets the customer requirements. Gold wire bonding delivered excellent results, meeting the customer specification. For the first prototypes we did get a total yield of 99.9%. The optical spectrum of the VCSELs and other measurements indicate that the assembly processes do not harm the diodes or their optical properties.

We present a very compact γ -detection module primarily designed for PET applications. On a total area of about 30 × 30 mm 2 , 144 SiPM photodetectors coupled to scintillator crystals are read out individually with fast timing ASICs. The core of the module is a LTCC ceramic substrate with internal water channels for efficient and stable liquid cooling. The top side of the LTCC is covered by 12×12 SiPMs in a regular pitch of 2.5 mm. The SiPMs are designed in the RGB-HD technology from FBK with a single cell size of 25 × 25 μ m 2 , very low dark-count rate and stable performance over a wide temperature range from 0 to 20 °C. The readout of the SiPMs is done with 4 specialized PETA5 ASICs flip-chip mounted to the bottom side of the substrate. Each chip has 36 readout channels (available in single or differential ended configuration) with self-triggered hit detection, a very low noise discriminator, signal amplitude integration and digitization, a TDC with 50 ps binwidth, neighbor logic and fast veto mechanisms. The full height of the assembly, including the connector to the main readout board, is less than 1 cm. In a 1:1 coupling configuration with 10 mm high LYSO scintillator arrays for detection of 511 keV gammas, the module has already reached 205 ps CRT time resolution (FWHM in coincidence between channels on two different modules), sufficient for ToF operation in PET. The module design, details on chip operation and latest results with LYSO arrays are described.

Electromigration comprises one of the processes affecting the long-term reliability of electronic devices; it has therefore been the focus of many investigations in recent years. In regards to flip chip packaging technology, the majority of published data is concerned with electromigration in solder connections to metallized organic substrates. Hardly any information is available in the literature on electromigration in lead-free solder connections on thin film ceramic substrates. This work presents results of a study of electromigration in lead-free (SAC305) flip chip solder bumps with a nominal diameter of 40 μm or 30 μm with a pitch of 100 μm on silicon chips assembled onto thin film Al2O3 ceramic substrates. The under bump metallization (UBM) comprised of a 5 μm thick electroless nickel immersion gold (ENIG) layer directly deposited on the AlCu0.5 trace. The ceramic substrates were metallized using a thin film multilayer (NiCr-Au(1.5 μm)-Ni(2 μm) structure on the top of which wettable areas were produced with high precision by depositing flash Au (60 nm) of the required diameter (40 μm or 30 μm). All electromigration tests were performed at the temperature of 125 °C. Initially, one chip assembly with 40 μm and one with 30 μm solder bumps was loaded with the current density of 8 kA/cm2 for 1,000 h. The assemblies did not fail and an investigation with SEM revealed no significant changes to the microstructure of the bumps. Thereafter seven chip assemblies with 40 μm solder bumps and five assemblies with 30 μm bumps were subjected to electromigration tests of 14 kA/cm2 or 25 kA/cm2, respectively. Six of the 40 μm-assemblies failed after 7,000 h and none of the 30 μm-assemblies failed after 2,500 h of test duration so far. Investigation of failed samples performed with SEM and EDX showed asymmetric changes of microstructure in respect to current flow. Several intermetallic phases were found to form in the solder. The predominant damage of the interconnects was found to occur at the cathode contact to chip; the Ni-P layers there showed typical columnar Kirkendall voids caused by migration of Ni from the layers into the solder. Failure of the contacts apparently occurred at the interface between Ni-P and solder. In summary, the results of the study indicate a very high stability of lead-free solder connections on ceramic substrates against electromigration. This high stability is primarily due to a better heat dissipation and thus to a relatively low temperature increase of the ceramic packages caused by resistive heating during flow of electric current. In addition, the type of the metallization used in the study seems to be more resistant to electromigration than the standard PCB metallization as it does not contain a copper layer.

We present recent advances in the technology for small form factor hybrid circuits with one water cooled LTCC substrate, Silicon Photomultipliers (SiPMs) and highest-performance ASICs for application in scintillator detectors for time-of-flight (TOF) Positron Emission Tomography / Magnetic Resonance Imaging applications. One of the biggest challenges is the development of miniaturized sensor modules that are highly functional and MRI compatible. The SiPM modules with an area of 32.8 by 32.0 mm2 contain 12 × 12 SiPMs in a pitch of 2.5 mm2. The readout of the 144 channels is performed by four PETA6 ASICs. The LTCC substrate with 2.1 mm thickness has been manufactured using the most advanced technologies developed at MSE. The liquid cooling channels inside the LTCC substrate provide excellent cooling for the ASICs, the SiPMs, and thermal insulation between ASICs and SiPMs and allow a very compact design of the detector modules, reducing their height by 50% compared with other technical solutions. The 12 SiPM arrays with 2×6 geometry are wire bonded only at the edges of the SiPMs to the LTCC, enabling the use of nearly the whole detector area for photon detection. At the opposite side of the substrate, four ASICs for the readout electronic with 272 μm bump pitch are flip-chip solder assembled to the LTCC substrate and underfilled and a few SMD components are mounted. LTCC substrates and all components are fully MRI compatible, which allows integration of PET with magnetic resonance imaging without mutual interference. A scintillator crystal array on top of the SiPMs converts gamma-rays produced by the decay of positrons into light. With measurements on prototypes the best coincidence resolving times (CRTs) for pairs of identical detectors in combination with high spatial resolution have been obtained.

Electromigration behaviour of Pb-free solder joints in flip-chip interconnects is usually studied in highly accelerated, short-term experiments using high current density and temperature. Failures typically occur in bumps which are in cathode contact at the chip side. There are only a few published studies in which Electroless Ni-P/Immersion Au (ENIG) surface finish was used as under-bump-metallization (UBM) structure, e.g. [5]. This paper deals with the long-term electromigration behaviour of Pb-free SAC305 flip-chip solder joints with a pitch of 100 μm and solder bump diameters of 50 μm or 60 μm, respectively. The ENIG surface finish was used on both the substrate and chip side. Test specimens were subjected to several levels of temperature and current density and tested up to 16,000 hours. The life time data is summarized using Weibull and lognormal distribution. The microstructure changes of interconnects in failed samples were subsequently investigated by SEM and EDX. Interconnects had failed due to consumption of Nickel, voids caused by electromigration, and Kirkendall void formation in the Ni-P-layer. The damage was asymmetric in respect to the current flow direction through the solder bumps and was most pronounced at the cathode side. Unexpectedly, however, the most severe damage occurred at the substrate and not at the chip side. We could show that - allowing for a few guidelines - lead-free flip-chip solder joints with 50 μm or 60 μm diameter have a sufficient electromigration life time for most applications.

In this study, accelerated life tests with ultra fine-pitch flip-chips with solder bumps down to 30 microns diameter have been performed. Tests commonly used like temperature cycling, high temperature storage, and humidity bias tests are not sufficient for such small packaging feature sizes any more. As solder bump sizes continue to decrease, along with the shrinkage of the solder pads and the scaling of line/space geometries, thermal diffusion has even more impact on reliability and lifetime of the solder connections, and current densities within single solder bumps increase. Therefore, electromigration of flip-chip interconnects is a significant reliability concern, especially when it comes to further miniaturization for high reliability applications. Since electromigration is a function of interconnect sizes and metallurgies, new interconnect developments need to be characterized for electromigration reliability. Flip-chips 10 mm × 10 mm × 0.8 mm in size with a die layout providing a pitch of 100 μm for solder bump sizes of 60 μm, 50 μm, 40 μm, or 30 μm diameter, respectively, have been used [1]. The SnAgCu alloy solder spheres were placed on a NiAu UBM realized in an electroless nickel process [2]. A daisy chain connection is integrated for each of the solder sphere sizes and each chip can separately be connected for online measurements during electromigration or reliability testing. A variety of current density and temperature combinations which is individually adapted to the respective solder sphere diameter has been used. Lifetime data were collected using online measurement through the daisy chains. Cross sectioning has been employed to analyze the influence of thermal diffusion as well as electromigration on the failure mechanism of the highly miniaturized solder joints. A prediction model for flip-chip interconnects with solder spheres down to 30 μm diameter will be outlined using Black’s equation.

The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process. To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide. The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1]. Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.

The aim of this research was to investigate the failure mechanism of lead-free (SAC305) flip-chip solder connections subjected to long-term electromigration. Interconnects with a nominal diameter of 60 µm or 50 µm were assembled in flip-chip organic packages with a pitch of 100 µm. The under bump metallization (UBM) and surface finish on PCBs comprised of a 5 µm thick electroless nickel immersion gold (ENIG) layer directly deposited on AlCu0.5 or Cu traces, respectively.

We present a very compact photo sensor module with an area of 32.8 × 32.0mm2 containing 12 × 12 Silicon Photomultipliers (SiPMs) in a pitch of (2.5mm)2. The readout of the 144 channels is done by highly specialized PETA5 ASICs (Position Energy Timing Asic) which offer self triggered hit detection (including neighbor logic and fast veto mechanisms), time stamping with 50ps bin width and digital amplitude measurement. The module uses a substrate which is cooled by a fluid running in internal channels. The SiPMs are glued and wire bonded in a regular pattern on the top side, the ASICs are flip chip mounted at the bottom side. Several modules will be plugged into a control and data readout PCB. The full height of these parts is below 1cm. The module can be used to read scintillator crystal arrays with a pitch of only 2.5mm in a 1 ∶ 1 coupling, or smaller crystals with light spreaders. We present the module design and the first results obtained with 1 ∶ 1 coupled LYSO crystal arrays.

Packaging technology has to continuously evolve in order to keep pace with the demand for smaller and lighter products. One manifestation of this is the need to drastically reduce the size of flip-chip bumps and their pitch. To make things more challenging, the changes have to be mastered with new materials in response to lead-free legislation. At the same time the reliability of the electronic devices should not be sacrificed. In this respect, a relatively new challenge is also posed by the observation, that solder connections are vulnerable to electromigration. The aim of this research was to evaluate the long-term electromigration behaviour of lead-free (SAC305) flipchip solder connections with a nominal diameter of 60 µm or 50 µm, which have been assembled in flip-chip organic packages having electroless Nickel under bump metallization with a pitch of 100 µm. Test vehicles were subjected to electromigration tests for over 25,000 hours at constant current densities of 8 kA/cm² or 5 kA/cm² respectively, and nominal temperatures of 125 °C, 100 °C, or 28 °C until failure. The failure data has been evaluated employing Weibull statistics as well as lognormal distribution and the mean time to failure (MTTF) has been calculated. Only three out of twelve samples have failed after 25,000 h for 50 µm solder bumps tested at a current density of 5 kA/cm² and a temperature of 100 °C; no failures at all have been observed at an ambient temperature of 28 °C. The comparison of the MTTFs for the different bump diameters leads to the result that, under the same testing conditions of current density and temperature, the life time of smaller bumps is considerably longer. This - on first sight - surprising finding can be explained by lower heat generation due to current flow, and thus by a lower temperature of these bumps. The results were subsequently used to estimate the parameters of Black’s equation. The evaluation yielded an activation energy of Ea = 1.13±0.18 eV and a current density exponent in the range of n = 4.9 - 2.2. The relatively high value of Ea points to a good robustness of the bump metallization investigated in our study; the variation of n indicates a change in failure mechanism.

Over the past five years, a great deal of work has been done to perform semiconductor die attach with AuSn alloys. Successful die attach has recently been achieved using Au and Sn multilayers evaporated onto the die or the host substrate. However, bonding techniques with thin (below 5 /spl mu/m) AuSn layers for very thin semiconductor devices have not yet been reported. The increasing demand for more advanced optoelectronic integrated circuits has created the need to bond materials having different lattice constants (e.g., GaAs on Si). In this paper we report a new way for the bonding of epitaxial liftoff (ELO) devices onto host substrates. Three of the multilayer structures investigated in this work produce a AuSn alloy bond with approximately 84 wt.% gold, but can be bonded with a peak temperature below 280/spl deg/C. The bonded samples were investigated with several standard surface analysis techniques: Optical microscopy, scanning electron microscopy (SEM), and energy dispersive X-ray analysis (EDX). We conclude that much thinner bonding layers can be attained than thus far reported. The results of our research allow us to optimize the layer structure and bonding parameters.

We present a gamma detection module optimized for very high resolution PET applications, able to resolve arrays of scintillating crystals with sub-millimeter pitch. The detector is composed of a single ceramic substrate (LTCC): it hosts four flip-chip mounted PETA5 ASICs on the bottom side and an array of SiPM sensors on the top surface, fabricated in HD-RGB technology by FBK. Each chip has 36 channels, for a maximum of 144 readout channels on a sensitive area of about 32 mm × 32 mm. The module is MR-compatible. The thermal decoupling of the readout electronics from the photon sensors is obtained with an efficient internal liquid channel, integrated within the ceramic substrate. Two modules have been designed, based on different SiPM topologies: • Light spreader-based: an array of 12 × 12 SiPMs, with an overall pitch of 2.5 mm, is coupled with a scintillators array using a 1 mm thick glass plate. The light from one crystal is spread over a group of SiPMs, which are read out in parallel using PETA5 internal neighbor logic.• Interpolating SiPM-based: ISiPMs are intrinsic position-sensitive sensors. The photon diodes in the array are connected to one of the four available outputs so that the center of gravity of any bunch of detected photons can be reconstructed using a proper weight function of the read out amplitudes. An array of ISiPMs, each 7.5 mm× 5 mm sized, is directly coupled with the scintillating crystals. Both modules can clearly resolve LYSO arrays with a pitch of only 0.833 mm. The detector can be adjusted for clinical PET, where it has already shown ToF resolution of about 230 ps CRT at FWHM. The module designs, their features and results are described.

The ongoing trend to miniaturized electronics has induced many developments towards size reduction and increasing performance in electronic products. To meet these requirements the involved processes, materials and components in electronics production have to be enhanced for high performance and high reliability. Flip-chip technology is one technology of choice with potential for highest integration. In previous investigations technologies for cost-efficient solder bumping and automated assembly in an industrial environment were evaluated. Wafer level solder sphere transfer and solder sphere jetting were adapted to provide flipchips with solder bump diameters down to 30 μm for flip-chip assembly onto printed circuit boards as well as onto thin film ceramic substrates. The reliability tests done so far showed excellent achievable reliability performance of these ultrafine-pitch assemblies under various test conditions. Since electromigration of flip-chip interconnects is a very important reliability concern, characterization of new interconnect developments needs to be done regarding the electromigration performance in accelerated life tests. For all experiments, specially designed flip-chips with 10 mm by 10 mm by 0.8 mm in size have been used. The silicon die layout provides a pitch of 100 μm with solder bump sizes between 60 μm and 30 μm in diameter. The solder spheres consist of lead-free SnAgCu alloy and are placed on a Ni-P under bump metallization which has been realized in an electroless nickel process. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements with separate daisy chain connections for each test coupon provide exact lifetime data during the electromigration tests, which are in some cases still in progress. Cross sectioning has been employed for the analysis of thermal diffusion as well as of the impact of electromigration influence on the failure mechanism using optical, SEM and EDX analysis, respectively. Reliability plots will be discussed regarding the electromigration performance for different test conditions applied to the respective test specimen for lifetime estimations.

The accelerated trend to smaller and lighter electronics has accentuated many efforts towards size reduction and increased performance in electronic products. However, equipment and processes of electronics production have to come along with this trend when it comes to connections on board level. The use of flip-chip bonding technology employing micro bumps for very fine pitch packaging is becoming increasingly important in the microelectronics industry. To meet these requirements, cost-efficient solder bumping and automated assembly technologies for the processing of flip-chips have been developed and qualified. Flip-chips used in this study show a pitch of 100 μm and solder ball diameter of 40 μm and 30 μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer (WLSST) process and solder sphere jetting (SB²) technology, respectively. The latter is a technique that has been used for many years in the wafer level packaging industry and is commonly known as a solder ball bumping tool. For the described work the SB² technology was scaled down for processing solder spheres with diameters of 30 μm with very good results achieved. Our research has shown that the underfill process is one of the most crucial factors when it comes to flip-chip miniaturization for high reliability applications. Therefore, a total of thirty different underfill materials were investigated initially in terms of flow time, gap height, filler sedimentation, and reliability. For reliability investigations, various standardized test conditions were applied to the test specimen. In previous experiments we found out that solder spheres of 50 μm seem to be the technological limit with current organic printed circuit board technology with subtractive structuring. Therefore, thin film ceramic as substrate material has been used showing excellent performance of the highly miniaturized solder joints at several reliability tests. Concluding long-term reliability and an analysis of the intermetallic growth are shown using SEM/EDX. Additionally, an analysis of the failure mechanism will be presented and recommendations for further miniaturization will be outlined. Advantages of the developed technology are lower cost compared to known techniques, very high flexibility and freedom in selection of solder composition including SAC, low melting alloys, gold-tin, and further special alloys.

The further miniaturization of electronic packages is driven by a large variety of applications with high requirements on pitch and form factor. This will be conducive to higher I/O-counts and a reduction of the solder bump size.

Reports results in the optimization of the bonding parameters, with different diffusion barriers, new multilayer structures, metallization of the transfer membrane, as well as new applications of our bonding technique. The bonded samples were investigated with several standard surface analysis techniques as well as mechanical tests. We achieved important improvements in reliability, yield, and in the planarity of the bonded devices. For a further enhancement of the bonding quality and to reduce the mechanical stress, induced by the mismatch of the coefficients of thermal expansion of the bonding partners, we investigated an annealing technique. The main advantages of our technology are thin bonding layers attained with a minimum use of gold and an outstanding bonding quality succeeded in the large temperature range between 235/spl deg/C and 286/spl deg/C without flux. A thin, void free AuSn bonding layer means low thermal resistance, which is especially important for laser diodes and high power devices: The threshold current of semiconductor laser diodes is very temperature sensitive. Further advantages of our new technique are the attainable precise control of the bonding layer thickness, which means very reproducible thermal resistance.

The increasing demand for more advanced photonic integrated circuits has created the need to combine semiconductor materials with different lattice constants, i.e., GaAs on Si. During the past few years, much has been reported concerning the epitaxial lift-off technique. The most widely reported bonding method of epitaxial lift-off films is van der Waals bonding. However, there are problems with van der Waals-bonded devices. For instance, it has a long bonding time, which hinders an industrial use. Recently, we have investigated refinements of the epitaxial lift-off and grafting technique through using a single, transparent polymer membrane to support the material during the etch of a sacrificial layer, then depositing Au and Sn multilayers onto the lifted off devices and new host substrate. The devices are bonded by applying heat and pressure in a reducing atmosphere. The multilayer structures investigated in this work produce a resulting AuSn alloy with approximately 84 wt.% gold, but can be bonded with a peak temperature of 235 degree(s)C. In this paper we report our results in the optimization of the bonding parameters, with different diffusion barriers, new multilayer structures, as well as new applications of our bonding technique. We achieved important improvements in reliability and yield. The main advantages of our technology are thin bonding layers achieved with a minimum use of gold and an outstanding bonding quality reached in the large temperature range between 235 degree(s)C and 286 degree(s)C without flux. A thin, void free bonding layer means low thermal resistivity, which is especially important for laser diodes and high power devices. Further advantages of our new technique are the attainable precise control of the bonding layer thickness and the possible alignment of the devices through the transparent support and bonding membrane. We applied our new bonding technique to different optoelectronic devices such as MQWs and commercial laser bars and have simultaneously bonded a large number of devices. The bonded samples were investigated with several standard surface analysis techniques like optical microscopy, scanning electron microscopy and energy dispersive X-ray analysis as well as mechanical tests.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.