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Fog computing has emerged as an extended version of the cloud infrastructure for providing latency-aware and scalable services for Internet of Things (IoT) devices. Adding the fog layer to the cloud computing paradigm improves the quality of service (QoS) of time-critical and delay-sensitive IoT applications. These applications consist of interconnected services that run on virtual machines (VM) or containers. Due to the resource-constrained nature of fog computing nodes and the interdependency of these VMs, the efficient placement of IoT applications has an impressive influence on the delay of IoT applications. Many IoT applications, such as industrial applications, health applications, smart cars, gaming applications, etc., are delay-sensitive. On the other hand, Distributed and heterogeneous features of fog nodes make it difficult to ensure the availability of these applications in fog environments. Unavailability in these applications (which is equivalent to infinite delay) can lead to irreparable loss. Therefore, various methods have been provided to ensure the availability of these applications. Using redundant VMs is an effective solution to ensure the availability of IoT applications. However, it is difficult to determine an efficient placement strategy for IoT applications that meet all of the required constraints of these applications in fog environments (such as resource constraints). As a result, this paper proposed a heuristic delay-efficient and availability-aware IoT application placement in fog environments called DAIP. DAIP tries to provide an application placement with low network delay to reduce applications delay. In addition, this method tries to provide an application placement with an acceptable level of availability. The DAIP is simulated using the iFogSim simulator. The simulations show that the DAIP method, in addition to ensuring the availability of applications, reduces network delay(and total delay) compared to the existing algorithms. [ABSTRACT FROM AUTHOR]

The performance growth in processors has been continuing toward increasing the number of processing cores on the chip and scaling the feature size of transistors. However, in the nanoera, side effects of the scaling, such as induced heterogeneities in the performance, power, and soft error rate of identically designed cores, prevent the potential performance from being fully utilized. In this paper, we harness the mentioned side effects in shared-memory multicore processors with unknown workloads by a dynamic heuristic scheduling algorithm called HDSAP. HDSAP aims to maximize performance, i.e., the average response time, under power and reliability constraints in presence of induced heterogeneities. In this regard, we use a mathematical model to quantify task to core assignments based on performance variation. We also consider the variation in power to change selected cores when the power constraint is missed. To meet the reliability constraint, we use N-modular redundancy while being aware of the variation in the soft error rate of cores to prevent under/over reliability estimation. To evaluate HDSAP, we run SPLASH benchmark suite on Sniper and MACPat simulators. As a result, the response time of HDSAP reduces by 6%, 8%, and 25% in comparison with similar algorithms under the same power and reliability constraints. [ABSTRACT FROM AUTHOR]

Graphics processing units (GPUs) are powerful in performing data-parallel applications. Such applications most often rely on the GPU's memory hierarchy to deliver high performance. Designing efficient memory hierarchy for GPUs is a challenging task because of its wide architectural space. To moderate this challenge, this paper proposes a framework, called stack distance-analytic modeling (SDAM), to estimate memory performance of the GPU in terms of memory cycle counts. Providing the input data to the model is crucial in terms of the accuracy of the input data, and the time spent to obtain them. SDAM employs the stack distance analysis method and analytical modeling to obtain the required input accurately and swiftly. Further, it employs a detailed analytical model to estimate memory cycles. SDAM is validated against real GPU executions. Further, it is compared with a cycle accurate simulator. The experimental evaluations, performed on a set of memory-intensive benchmarks, prove that SDAM is faster and more accurate than cycle-accurate simulation, thus it can facilitate the GPU cache design-space exploration. For a selection of data-intensive benchmarks, SDAM showed a 32% average error in estimating memory data transfer cycles in a modern GPU, which outperforms cycle-accurate simulation, while it is an order of magnitude faster than the cycle-accurate simulation. Finally, the applicability of SDAM in exploring cache design-space in GPUs is demonstrated through experimenting with various cache designs. [ABSTRACT FROM AUTHOR]

• Scheduling IoT service by hybrid optimization of Particle Swarm and Chemical Reaction. • Offline resource provisioning in an environment comprising both fog and cloud servers. • Minimizing service delay and delay violation by provisioning on faster nodes. • Minimizing communication traffic load between servers due to offloading tasks. • Requiring minimum information about services by aggregating incoming traffic to nodes. This paper addresses the escalating challenges posed by the ever-increasing data volume, velocity, and the demand for low-latency applications, driven by the proliferation of smart devices and Internet of Things (IoT) applications. To mitigate service delay and enhance Quality of Service (QoS), we introduce a hybrid optimization of Particle Swarm (PSO) and Chemical Reaction (CRO) to improve service delay in FogPlan, an offline framework that prioritizes QoS and enables dynamic fog service deployment. The method optimizes fog service allocation based on incoming traffic to each fog node, formulating it as an Integer Non-Linear Programming (INLP) problem, considering various service attributes and costs. Our proposed algorithm aims to minimize service delay and QoS degradation. The evaluation using real MAWI Working Group traffic data demonstrates a substantial 29.34% reduction in service delay, a 66.02% decrease in service costs, and a noteworthy 50.15% reduction in delay violations compared to the FogPlan framework. [Display omitted] [ABSTRACT FROM AUTHOR]

Modern GPUs can execute multiple kernels concurrently to keep the hardware resources busy and to boost the overall performance. This approach is called simultaneous multiple kernel execution (MKE). MKE is a promising approach for improving GPU hardware utilization. Although modern GPUs allow MKE, the effects of different MKE scenarios have not adequately studied by the researchers. Since cache memories have significant effects on the overall GPU performance, the effects of MKE on cache performance should be investigated properly. The present study proposes a framework, called RDMKE (short for Reuse Distance-based profiling in MKEs), to provide a method for analyzing GPU cache memory performance in MKE scenarios. The raw memory access information of a kernel is first extracted and then RDMKE enforces a proper ordering to the memory accesses so that it represents a given MKE scenario. Afterward, RDMKE employs reuse distance analysis (RDA) to generate cache-related performance metrics, including hit ratios, transaction counts, cache sets and Miss Status Holding Register reservation fails. In addition, RDMKE provides the user with the RD profiles as a useful locality metric. The simulation results of single kernel executions show a fair correlation between the generated results by RDMKE and GPU performance counters. Further, the simulation results of 28 two-kernel executions indicate that RDMKE can properly capture the nonlinear cache behaviors in MKE scenarios. [ABSTRACT FROM AUTHOR]

Abstract Memory footprint is a metric for quantifying data reuse in memory trace. It can also be used to approximate cache performance, especially in shared cache systems. Memory footprint is acquired through memory footprint analysis (FPA). However, its main limitation is that, for a memory trace of n accesses, the all-window FPA algorithm requires O (n 3) time. Therefore, in this paper, we propose an analytical algorithm for FPA, whereby the average footprints are calculated in O (n 2). The proposed algorithm can also be employed for window distribution analysis. Moreover, we propose a framework to enable the application of FPA to GPU kernels and model the performance of L1 cache memories. The results of experimental evaluations indicate that our proposed framework functions 1.55X slower than the Xiang's formula, as a fast average FPA method, while it can also be utilized for window distribution analysis. In the context of FPA-based cache performance estimation, the experimental results indicate a fair correlation between the estimated L1 miss rates and those of the native GPU executions. On average, the proposed framework has 23.8% error in the estimation of L1 cache miss rates. Further, our algorithm runs 125X slower than the reuse distance analysis (RDA) when analyzing a single kernel. However, the proposed method outperforms RDA in modeling shared caches and multiple kernel executions in GPUs. [ABSTRACT FROM AUTHOR]

Recent years have seen a rise in the popularity of the Internet of Things (IoT) and its applications, due to its adaptability, usability, varied application potential, and ease of deployment. On the other hand, security threats get more attention. Where wireless sensor networks (WSN), which is the core of IoT, are vulnerable to the jammer's attack due to the fact that they are shared and have open access to a wireless channel. Moreover, the difficult conditions in which nodes are distributed, such as underwater, fires, volcanoes, animal habitats, or battlefields, node localization is a significant challenge for the majority of WSN applications. Additionally, the lack of accuracy in traditional localization algorithms has prompted researchers to propose optimization techniques capable of improving localization accuracies, such as genetic algorithms, gravitational search algorithms, neural networks, and deep learning; however, these techniques require additional hardware to perform their complex calculations. On the other side, uncomplicated algorithms like Virtual Force Iteration Localization (VFIL), Weighted Centroid Localization (WCL), and Centroid Localization (CL) are less accurate. To bridge that gap, this work proposes a lightweight algorithm for accurately locating the jammer's coordinates. Our algorithm consists of three phases firstly, a simple way to detect a jamming attack. Second novel designed technique to draw the jammed region using the mapping protocol. Moreover, a range-free technique is proposed to locate the jammer based on geometric calculations. Finally, A set of simulation experiments was undertaken to assess the suggested algorithm's performance. Experiments reveal that the suggested method is capable of precisely locating the jammer. Additionally, the presented method demonstrates superior efficiency in comparison to existing methods. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents a behavioral-based error detection technique called control flow checking by execution tracing (CFCET) to increase concurrent error detection capabilities of commercial off-the-shelf (COTS) processors. This technique traces the program jumps graph (PJG) at run-time and compares it with the reference jumps graph to detect possible violations caused by transient faults. The reference graph is driven by a preprocessor from the source program. The idea behind the CFCET is based on using an external watchdog processor (WDP) and also the internal execution tracing feature available in COTS processors to monitor the addresses of taken branches in a program, externally. This is done without any modification of application programs, thus, the program overhead is zero. This technique is analytically evaluated based on three different fault models. The results show that the error detection coverage varies between 79.74% and 96.43% depending on the different workload programs. The errors are detected with about zero latency. The external hardware overhead is about 3% using the Altera flex 10K30 FPGA and the execution time overhead is between 33.26% and 140.81% for different workload programs. The overheads have been measured experimentally by executing the workloads on a Pentium system. [Copyright &y& Elsevier]

Abstract: This paper presents a software-based error detection scheme called enhanced committed instructions counting (ECIC) for embedded and real-time systems using commercial off-the-shelf (COTS) processors. The scheme uses the internal performance monitoring features of a processor, which provides the ability to count the number of committed instructions in a program. To evaluate the ECIC scheme, 6000 software induced faults are injected into a 32-bit Pentium® processor. The results show that the error detection coverage varies between 90.52% and 98.18%, for different workloads. [Copyright &y& Elsevier]

The rapid growth of current computer networks and their applications has made network traffic classification more important. The latest approach in this field is the use of deep learning. But the problem of deep learning is that it needs a lot of data for training. On the other hand, the lack of a sufficient amount of data for different types of network traffic has a negative effect on the accuracy of the traffic classification. In this regard, one of the appropriate solutions to address this challenge is the use of data fusion methods in decision level. Data fusion techniques make possible to achieve better results by combining classifiers. In this paper, a network traffic classification approach based on deep learning and data fusion techniques is presented. The proposed method can identify encrypted traffic and distinguish between VPN and non-VPN network traffic. In the proposed approach, first, a preprocessing on the dataset is carried out, then three deep learning networks, namely, Deep Belief Network, Convolution Neural Network, and Multi-layer Perceptron to classify network traffic are employed. Finally, the results of all three classifiers using Bayesian decision fusion are combined. The experimental results on the ISCX VPN-nonVPN dataset show that the proposed method improves the classification accuracy and performs well on different network traffic types. The average accuracy of the proposed method is 97%. [ABSTRACT FROM AUTHOR]

Software solutions are not effective to be used in network applications because of their low throughput. By employing hardware implementation on FPGA, not only sufficient flexibility is achieved but also the throughput is increased considerably. In this paper, two multi-core architectures are proposed for Bloom filter and CRC as two main network processing core functions. These architectures called multi-core architecture with shared queue and multi-core architecture with private queue. The proposed architectures are implemented for 1, 2, 4, 8 and 16 cores. Experimental results show that multi-core architecture with private queue achieves higher throughput In comparison to the other one. As compared to Bloom filter, CRC application leads to less computational load and consequently more throughput. Moreover, Bloom filter is implemented on GPU and CPU and the results are compared with each other. When number of packets in GPU memory is 16384, the speedup achieved by GPU implementations using CUDA is about 274 times compared with CPU implementations. However, FPGA results outperform GPU, so that the throughput of the first architecture (shared queue) and second architecture (private queue) with 16 cores are almost 5.5 and 7.1 times higher than GPU throughput, respectively. [ABSTRACT FROM AUTHOR]