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A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of 433.80 μV/mA and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of 1 μs. The total current consumption is 17.88 μA (for a 0.9 V supply voltage). [ABSTRACT FROM AUTHOR]

The design and implementation of three analog median filter topologies, whose transistors operate in the deep weak-inversion region, is described. The first topology is a differential pairs array, in which drain currents are driven into two nodes in a differential fashion, while the second topology is based on a wide range OTA, which is used to maximize the dynamic range. Finally, the third topology uses three range-extended OTAs. The proposed weak-inversion filters were designed and fabricated in ON Semiconductor 0.5 µm technology through MOSIS. Experimental results of three-input fabricated prototypes for all three topologies are shown, with power consumptions of 90 nW in the first case, and 270 nW in the other two cases. A dual power supply ±1.5 Volts was used. [ABSTRACT FROM AUTHOR]

A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 μm CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 μW). [ABSTRACT FROM AUTHOR]

Different design procedures to operate MOS translinear loops at low supply voltage are presented. They utilize innovative biasing strategies based on flipped voltage followers and floating batteries. An alternate topology based on coupled negative feedback loops is also introduced. Simulation and measurement results for various test chip prototypes validate the proposed techniques and allow comparison among them. [ABSTRACT FROM AUTHOR]

A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage-to-current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 μm CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 μA/V to 165 μA/V) and a total harmonic distortion of -67 dB at 1 MHz for an input of 1 Vpp and a supply voltage of 1.8 V. [ABSTRACT FROM AUTHOR]

A technique to achieve highly linear scaling of differential currents in CMOS technology is presented. It is based on operation in weak or moderate inversion, and features performance improvements over previous proposals aimed to the same goal, like reduced supply voltage requirements, increased power efficiency, and avoidance of bulk effect. As an example, this technique is applied to attain continuous tuning for two novel voltage-to current converters, achieving highly linear programmable transconductance over a rail to-rail input range. Both implementations fabricated in a O.5-ඵtm CMOS technology using a dual supply of ±1.5 V achieve a THD of -60 dB with differential input swings of 6 Vpp (i.e., twice the supply voltage). The area and power consumption are 0.12 mm2 and 2.6 mW for the first implementation and 0.11 mm2 and 2.2 mW for the second one, respectively. [ABSTRACT FROM AUTHOR]

A high-performance CMOS winner-take-all circuit based on the differential flipped voltage follower is introduced. Simulations demonstrate the potential of the circuit to operate at very high speed, with high precision even for close input values and with low supply voltages. Experimental verification of the circuit is provided in a 0.5-μm CMOS technology. [ABSTRACT FROM AUTHOR]

A new family of single-stage super Class-AB operational transconductance amplifiers (OTAs) suitable for low-voltage operation and low power consumption is presented. Three novel topologies are proposed featuring simplicity and compactness. They are based on the combination of adaptive biasing techniques for the differential input stage and nonlinear current mirrors for the active load that provide additional dynamic current boosting. The OTAs have been fabricated in a standard 0.5-μm CMOS process. Experimental results show a greatly improved slew rate by factors 30–60 and gain-bandwidth product by factors 11.5–17 when compared to a classical Class-A OTA. The circuits are operated at ±1-V supply voltage with only 10 μA of bias current. [ABSTRACT FROM AUTHOR]

A simple and efficient low-voltage two-stage operational amplifier with Class-AB output stage is introduced. It has a large effective output current boosting factor (∼50) and close to a factor 2 bandwidth enhancement. This is achieved at the expense of minimum increase in circuit complexity and no additional static power dissipation. Experimental verification of the characteristics of the proposed circuit is provided. [ABSTRACT FROM AUTHOR]