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224 results on '"Raman, Ashish"'

4. A New Approach to Improve Reliability in UART Using Checksum Algorithm

Author

Rathore, Kshitiz, Khosla, Mamta, Raman, Ashish, Kacprzyk, Janusz, Series Editor, Gomide, Fernando, Advisory Editor, Kaynak, Okyay, Advisory Editor, Liu, Derong, Advisory Editor, Pedrycz, Witold, Advisory Editor, Polycarpou, Marios M., Advisory Editor, Rudas, Imre J., Advisory Editor, Wang, Jun, Advisory Editor, Reddy, K. Ashoka, editor, Devi, B. Rama, editor, George, Boby, editor, Raju, K. Srujan, editor, and Sellathurai, Mathini, editor

Published
2023
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5. Modified VHDL Implementation of 128-Bit Rijndael AES Algorithm by Asymmetric Keys

Author

Das, Soham, Kashyap, Nitesh, Raman, Ashish, Kacprzyk, Janusz, Series Editor, Gomide, Fernando, Advisory Editor, Kaynak, Okyay, Advisory Editor, Liu, Derong, Advisory Editor, Pedrycz, Witold, Advisory Editor, Polycarpou, Marios M., Advisory Editor, Rudas, Imre J., Advisory Editor, Wang, Jun, Advisory Editor, Reddy, K. Ashoka, editor, Devi, B. Rama, editor, George, Boby, editor, Raju, K. Srujan, editor, and Sellathurai, Mathini, editor

Published
2023
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11. Pentacene-Based Hybrid Photodetectors: A Review

Author

Tripathi, Saumya, Raman, Ashish, Sunkaria, Ramesh Kumar, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Oneto, Luca, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Dhawan, Amit, editor, Mishra, R. A., editor, Arya, Karm Veer, editor, and Zamarreño, Carlos Ruiz, editor

Published
2022
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12. Design of Low-Power Bit Swapping BIST for IC Self-testing

Author

Gupta, Kanika, Raman, Ashish, Kacprzyk, Janusz, Series Editor, Gomide, Fernando, Advisory Editor, Kaynak, Okyay, Advisory Editor, Liu, Derong, Advisory Editor, Pedrycz, Witold, Advisory Editor, Polycarpou, Marios M., Advisory Editor, Rudas, Imre J., Advisory Editor, Wang, Jun, Advisory Editor, Saini, H. S., editor, Singh, R. K., editor, Tariq Beg, Mirza, editor, Mulaveesala, Ravibabu, editor, and Mahmood, Md Rashid, editor

Published
2022
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31. Effect of AlN Spacer Layer on the Proposed MIS-AlGaN/GaN HEMT

Author

Ranjan, Ravi, Kashyap, Nitesh, Raman, Ashish, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zhang, Junjie James, Series Editor, Mallick, Pradeep Kumar, editor, Meher, Preetisudha, editor, Majumder, Alak, editor, and Das, Santos Kumar, editor

Published
2020
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32. High-Frequency CNTFET-Based Voltage-Controlled Oscillator for PLL Application

Author

Kumar, Yogesh, Raman, Ashish, Ranjan, Ravi, Sarin, R. K., Kacprzyk, Janusz, Series Editor, Gomide, Fernando, Advisory Editor, Kaynak, Okyay, Advisory Editor, Liu, Derong, Advisory Editor, Pedrycz, Witold, Advisory Editor, Polycarpou, Marios M., Advisory Editor, Rudas, Imre J., Advisory Editor, Wang, Jun, Advisory Editor, Sharma, Devendra Kumar, editor, Balas, Valentina Emilia, editor, Son, Le Hoang, editor, Sharma, Rohit, editor, and Cengiz, Korhan, editor

Published
2020
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39. A Comprehensive Analysis of Nanosheet Field-Effect Transistor: Recent Advances and Comparative Study.

Author

Chauhan, Abhishek and Raman, Ashish

Subjects
*FIELD-effect transistors, *ELECTROSTATICS, *COMPARATIVE studies, *DOPING agents (Chemistry)
Abstract

In this paper for the first time, we have studied various structures of nanosheet field-effect transistors (NSFET) and the effect of various devices and process parameters such as nanosheet width, length, interspacing, S/D doping, channel doping, random dopant fluctuations studied on these device structures. Comparative analysis has been done between JL-NSFET, GS-JL-NSFET, JL-SiGeNSFET and JL-GS-SiGeNSFET in terms of analog parameters. Nanosheet-based FETs are likely to be the successor of FinFET beyond the 5-nm node. NSFETs have better control over gate, variable sheet width and more current per device footprint which gives them the advantage of circuit design versatility. NSFET offers better gate control, better current and switching per device footprint. NSFETs are preferred over NWFETs due to better electrostatics, greater channel widths, decreased SCEs and increased device reliability. [ABSTRACT FROM AUTHOR]

Published
2024
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49. High Speed Reconfigurable FFT Design by Vedic Mathematics

Author

Raman, Ashish, Kumar, Anvesh, and Sarin, R. K.

Subjects
Computer Science - Other Computer Science
Abstract

The Fast Fourier Transform (FFT) is a computationally intensive digital signal processing (DSP) function widely used in applications such as imaging, software-defined radio, wireless communication, instrumentation. In this paper, a reconfigurable FFT design using Vedic multiplier with high speed and small area is presented. Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized to improve its efficiency. In the proposed architecture, the 4x4 bit multiplication operation is fragmented reconfigurable FFT modules. The 4x4 multiplication modules are implemented using small 2x2bit multipliers. Reconfigurability at run time is provided for attaining power saving. The reconfigurable FFT has been designed, optimized and implemented on an FPGA based system. This reconfigurable FFT is having the high speed and small area as compared to the conventional FFT., Comment: Submitted to Journal of Computer Science and Engineering, see http://sites.google.com/site/jcseuk/volume-1-issue-1-may-2010

Published
2010

50. Differential RVCO with low power, low phase noise and wider tuning range for PLL application.

Author

Kumar, Yogesh, Raman, Ashish, Ranjan, Ravi, Deep, Shekhar, and Sarin, Rakesh Kumar

Subjects
*PHASE noise, *VOLTAGE-controlled oscillators, *DESIGN exhibitions, *PHASE-locked loops
Abstract

A differential ring CMOS voltage-controlled oscillator (VCO) with dual-delay path topology is proposed in this paper. In this work, the focus area is to improve the tuning range of VCO and phase noise performance of the VCO. The dual-delay path topology is used with P-MOS as load in series with negative-skewed delay transistors. This design gives the wider tuning range and this increases the phase noise performance of the VCO. After the post-layout simulation, frequency tuning range and power dissipation range are 730 MHz to 2.81 GHz and from 1.32 mW to 4.62 mW respectively. The phase noise for this VCO is −97.35 dBc/Hz at 1 MHz offset. The technology used in this work was taken from the library of SCL 180 nm technology. This design exhibits excellent phase noise performance. [ABSTRACT FROM AUTHOR]

Published
2024
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