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An imaging pixel unit-cell topology leveraging a photodetector in the forward-bias region is proposed. Connecting the anode of the photodiode to the gate of a NMOS device operating in the subthreshold region provides the basis for a new open-circuit voltage pixel (VocP) architecture. Theoretical analysis is presented to show the response and performance benefits of the VocP in comparison to a conventional pixel. Based on this analysis, the signal and noise relationships for both pixels are derived and leveraged to construct an end-to-end readout system model. The model results highlight potential performance benefits of the VocP over a conventional direct-injection pixel topology. To verify the analysis, the proposed VocP readout architecture is fabricated along with a conventional direct-injection pixel readout in a $0.18~\mathrm {\mu }\text{m}$ CMOS technology. The VocP performance is compared to a traditional reverse-bias current-mode photodetector configuration. Simulation, modeling, and measurements align with the proposed analytical model. Benefits in system sensitivity and dynamic range are demonstrated showing more than a $2\times $ improvement in noise-equivalent temperature difference and a 4 dB improvement in dynamic range.

This paper presents a highly linear BiCMOS sample and hold amplifier (SHA) providing 2.8-GS/s intermediate frequency (IF) sampling for a 1-GHz input bandwidth spanning from 1.5 to 2.5 GHz. A single-transistor hold-mode feedthrough cancellation technique is implemented to remove distortion resulting from the nonlinear parasitic capacitance at the sampling node. The SHA is designed in a mainstream 130-nm BiCMOS technology using SiGe heterojunction bipolar transistors to buffer and sample the wideband input. The proposed SHA enables monolithic integration with a high-speed analog-to-digital converter core to realize a high-performance converter solution. This independent sampling front end occupies a core chip area of 0.6 mm2 and consumes an average power of 1.26 W. The SHA is a pseudo-differential open-loop design that includes two cascaded track-and-hold amplifiers, a high-speed clock driver, and externally adjustable current mirror biases. The high-speed clock drivers and buffers add 170 mW to the total power consumption. The measurements of the fabricated SHA show a 10-bit effective resolution across the 1-GHz IF bandwidth and < −61-dBc HD2 and HD3.

Unlike conventional detectors that rely on photocurrent, the open circuit voltage photodetector architecture relies on a detector operating in zero bias. The output from the detector is coupled to the gate of a FET in sub-threshold region. Radiometric characterization of this detector will be discussed.

Strong motivation for low-cost infrared imaging devices over the past few years have given rise to advances in infrared detector technology, specifically in the mid-wave infrared (MWIR) region. With increasing demand for small pixel sizes and large format focal plane arrays (FPAs), the extreme complexity in realizing MWIR imagers is expected to increase in difficulty. In this work, a novel approach to provide improved infrared detection at high operating temperatures is proposed by integrating proven MWIR photovoltaic material and mature digital CMOS Image Sensor (CIS) technology in a resultant technology concept of an open circuit voltage photodetector (VocP). With this new approach to photon detection, the photosensitive material generates an open circuit voltage to control the drain current of a transistor. The drain current can then be considered the photocurrent in the proposed pixel design. The VocP design decouples the photocurrent from the pixel area, exploits the invariance of open circuit voltage to pixel dimensions, improves the detectors dark current, and results in higher sensitivity. The proposed approach also couples an infrared sensitive material to CIS technology that is well established and continues to be advanced for visible imagers. In this paper, initial research demonstrations and test results are presented to provide evidence of MWIR detection at high operating temperatures to prove the concept and modeling predictions for the sensitivity and dynamic range of VocP.

We theoretically and experimentally investigate the application of an open-circuit voltage photodetector (VocP) architecture for mid-wave infrared (MWIR, 3–5 μm) detection and imaging. In contrast to conventional reverse-bias (RB) operation of the diode, which generates a photocurrent that is proportional to the photon irradiance, we evaluate the potential of using unbiased diodes that generate an open-circuit voltage, VOC, under illumination. The predicted Noise Equivalent Differential Temperature (NEDT) of a VocP is inferior to conventional RB when we assume an infinite well capacity and fixed integration time, but the prediction reverses when the actual well capacity of a readout integrated circuit (ROIC) is taken into account. Therefore, for a focal plane array (FPA) with a ROIC, we predict superior NEDT for the VocP. To demonstrate this concept, we fabricated and tested a basic VocP unit-cell architecture by connecting the VOC anode of a MWIR photodiode to the gate of an n-type metal-oxide semiconductor transistor that is operated in sub-threshold. Very good agreement is obtained between the analytical model and the observed drain current of the transistor over three orders of photon irradiance (1015–1018 photons/sec-cm2). The decoupling of the diode photocurrent from the integration capacitor in the circuit leads to a lower dark current that allows for longer integration times and improved sensitivity. This potentially can have a great impact on the performance and functionality of FPAs, leading to FPAs with better NEDT at a higher operating temperature, wider dynamic range, and smaller pixel size leading to larger array formats.

This article presents a highly linear BiCMOS sample and hold amplifier (SHA) providing 2.8 GS/s intermediate frequency (IF) sampling for a 1 GHz bandwidth input spanning from 1.5 GHz to 2.5 GHz. A single-transistor hold-mode feedthrough cancellation technique is implemented to remove the distortion resulting from the nonlinear parasitic capacitance at the sampling node. The SHA is designed in a mainstream 130 nm BiCMOS technology using SiGe heterojunction bipolar transistors (HBTs) to buffer and sample the wide-band input. Potential inclusion of this BiCMOS SHA in a subsequent high-speed ADC design provides the possibility for a monolithic high performance converter solution. This independent sampling front-end occupies a core chip area of 0.6 mm2. The SHA is a pseudo-differential open-loop design that includes two cascaded track-and-hold amplifiers (THA), a high-speed clock driver, and externally adjustable current mirror biases. Measurements of the fabricated SHA show a 10-bit effective resolution across the 1 GHz bandwidth and > 61 dBc spurious free dynamic range (SFDR).

A CMOS SRAM design in 130 nm BiCMOS SiGe technology is presented. A 10Kb array was designed to operate at a 500 MHz clock and a 1.5 V supply. The SRAM array is implemented in four 2.5Kb quadrants with shared column and row addresses and local quadrant decoding. A calibrated and tunable replica timing structure technique is used to generate optimal sense amplifier (SA) enable timing by replicating both column and row delay of the memory simultaneously using replica bitline and replica wordline structures. A new capacitive offset cancellation technique for current-mode SA is proposed. Using replica timing and capacitive offset cancellation techniques optimizes operation speed for the most process-invariant timing and smallest SA area. Monte Carlo simulations were performed on both the current mode sense amplifier with capacitive offset cancellation (CSAcoc), and a conventional latch type CSA without offset cancellation for 200 runs of process and mismatch. The CSAcoc performed without read failures across the design space at ∼100ps faster read access time with 50% less SA area.

This paper compares the performance of three low drop-out (LDO) voltage regulators (simple LDO, LDO with common-source, and LDO with source-follower) in load regulation and transient response. The regulators are designed in 1.6 /spl mu/m technology with three different error amplifier designs to investigate the regulating performance. The performance of each architecture is verified by simulation results.