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We investigated the effect of using a synthetic ferrimagnetie (SyF) free layer in MgO-based magnetic tunnel junctions (MTJs) on current-induced magnetization switching (CIMS), particularly for application to spin-transfer torque random access memory (SPRAM). The employed SyF free layer had a [Co.sub.40][Fe.sub.40][B.sub.20]/Ru/[Co.sub.40][Fe.sub.40][B.sub.20] and [Co.sub.20][Fe.sub.60][B.sub.20]/Ru/[Co.sub.20][Fe.sub.60][B.sub.20] structures, and the MTJs (100 x (150-300) [nm.sup.2]) were annealed at 300 [degrees]C. The use of SyF free layer resulted in low intrinsic critical current density ([J.sub.c0]) without degrading the thermal-stability factor (E/[[kappa].sub.B]T, where E, [[kappa].sub.B], and T are the energy potential, the Boltzmann constant, and temperature, respectively). When the two CoFeB layers of a strongly antiferromagnetieally coupled SyF free layer had the same thickness, [J.sub.c0] was reduced to 2-4 x [10.sup.6] A/[cm.sup.2]. This low [J.sub.c0] may be due to the decreased effective volume under the large spin accumulation at the CoFeB/Ru. The E/[[kappa].sub.B]T was over 60, resulting in a retention time of over ten years and suppression of the write current dispersion for SPRAM. The use of the SyF free layer also resulted in a bistable (parallel/antiparallel) magnetization configuration at zero field, enabling the realization of CIMS without the need to apply external fields to compensate for the offset field. Index Terms--CoFeB, current-induced magnetization switching, MgO barrier, synthetic ferrimagnetie free layer.

A characteristic temperature dependence of FN-induced erase-level shift in sub-90-nm-node embedded split-gate polysilicon/oxide/nitride/oxide/silicon (SONOS) memory is discussed. Results concluded that [V. sub. T] rise at 25 degree celcius and falls at 90 degree celcius.

The nitrogen composition dependence of the characteristics of TaN/HfLaON/[Hf.sub.1-x-y][N.sub.x][O.sub.y]/Si[O.sub.2]/Si MONOS memory devices is discussed. A wider memory window and a smaller high-temperature decay rate are observed in the [Hf.sub.0.3][N.sub.0.2][O.sub.0.5] MONOS devices.

The fabrication of the resistive random access memory with NiO resistive memories and control transistors by using the CMOS technology is discussed. The devices are shown to exhibit a sub-100-[mu]A reset current and hence can easily be used as a highly reliable, nonvolatile memory source.

The fabrication of one-transistor-capacitor structure of a nonvolatile thin film transistor (TFT) ferroelectric RAM (FeRAM) devices using the Ba([Zr.sub.0.1][Ti.sub.o.9])[O.sub.3] gated oxide film is explained.

The development of a 10-kA/[cm.sup.2] Nb multi-layer fabrication process composed of more than six planarized Nb layers, an Nb/Al[O.sub.x]/Nb junction layer, a Mo resistor layer, and Si[O.sub.2] insulator layers which could achieve larger scale and higher speed single flux quantum (SFQ) circuits is reported.

A three-dimensional simulation model was used to study the switching dynamics associated with reset and set operations of vertical phase change random access memory (PCRAM) cells. The results reveal that threshold conditions for reset and set operations were observed to depend on the crystallization, melting and amorphization dynamics at this interface which are in close agreement with existing experimental data.

The numerical simulation of a novel, nonvolatile memory device based on a conductive ferroelectric/semiconductor thin film multilayer stack is presented. The results have shown that the potential distribution in an acceptor-doped ferroelectric thin film is affected by the orientation of the polarization, if top and bottom electrodes differ in the work function.

The fast Vth instability in Hf[O.sub.2] gate dielectric MOSFETs and its impact on digital circuits is characterized and modeled. [DELAT]Vth due to fast charge trapping is shown to be predictable in both static and dynamic stress situations, while the use of certain circuit designs are demonstrated to take advantage of the dynamic nature of charge-trapping effect in a deterministic manner potentially allowing the performance of logic circuit to be less affected by fast Vth instability.

Fault-tolerant memory systems (FTM) were proposed for high-capacity memories based on divided bit-line, and divided word-line structures. Experimental results revealed that if the number of detected faults was large for a memory array, one could use more row or column banks to enhance the repair rate and yield.

The combination of synchrotron muXRF/muXRD microfocus experiments demonstrates the integration process steps enabling to fabricate ferroelectric capacitors offering good performance using conventional complementary metal-oxide-semiconductor fabrication processes. The study suggests that the formation of a polycrystalline ferroelectric film is with well-controlled microstructure after the transistor fabrication.

A 0.18 mum CMOS technology is used for the development of a nondestructive readout (NDRO) ferroelectric random access memory (FeRAM). The correction in the process variations in threshold voltage of neighboring readout transistors results in a wide NDRO operation margin over a supply voltage range from 1.1 to 1.8 V.

The magnetization dynamic in ferromagnetic heterostructures from first principles, focusing on the role of spin pumping in layered structures is reviewed. It is based on the assumption of semiclassical transport in bulk materials that is valid for diffuse and chaotic systems, as well as a separation of time scales of the electronic and magnetic degrees of freedom.

In this paper, three generic RAM-based architectures are proposed to efficiently construct the corresponding two-dimensional architectures by use of the line-based method for any given hardware architecture of one-dimensional (1-D) wavelet filters, including conventional convolution-based and lifting-based architectures. An exhaustive analysis of two-dimensional architectures for discrete wavelet transform in the system view is also given. The first proposed architecture is for 1-level decomposition, which is presented by introducing the categories of internal line buffers, the strategy of optimizing the line buffer size, and the method of integrating any 1-D wavelet filter. The other two proposed architectures are for multi-level decomposition. One applies the recursive pyramid algorithm directly to the proposed 1-level architecture, and the other one combines the two previously proposed architectures to increase the hardware utilization. According to the comparison results, the proposed architecture outperforms previous architectures in the aspects of line buffer size, hardware cost, hardware utilization, and flexibility. Index Terms--Discrete wavelet transform (DWT), lifting scheme, line-based method, recursive pyramid algorithm, VLSI architecture.

The Pb(Zr,Ti)O3 (PZT) film composition for highly reliable ferroelectric random access memory (FeRAM) application is investigated. Optimum composition Zr/Ti = 30/70 provides maximum operational margin.

Multiple-power-level ALOHA has been proposed to take advantage of the capture phenomenon in order to improve the throughput of a multiple random access system. In this paper, we study the effect of the use of multiple transmission power levels and of the corresponding packet lengths on the system throughput and energy efficiency. We prove that the single-power-level system in which all transmit at the maximum allowable power level achieves both optimal throughput and energy usage efficiency under a condition on the decodability threshold value. Index Terms--ALOHA, capture, energy efficiency, random access.

A new superconductor single flux quantum (SFQ) random access memory (RAM) which uses single flux quanta both for storage and retrieval of data is developed. The new design has only 2 Josephson junctions per cell, thus allowing very dense designs. It also employs ballistic transfer of SFQ pulses along bit lines to perform read and write operations. Further improvements in the RAM's performance is possible if an advanced fabrication process with high-area Josephson functions could be found.

Giant magnetoresistance (GMR) materials are used for random access, non-volatile memories. Different memory architectures have been proposed, both using GMR multilayers and spin-valve (SV) sandwich structures. In most of these approaches extra word lines are needed for writing purposes in addition to read contacts. This makes three interconnect levels. We show results on a simpler SV memory architecture, where writing is achieved using the read current contacts. This is relevant in terms of fabrication, as only two interconnecting layers are necessary to address a matrix of bits. A 400 bit memory matrix was fabricated and tested. A 2 mV signal between '0' and '1' states was measured for a bit inside this matrix.

A storage mechanism in ferromagnetic-insulator-ferromagnetic spin-polarized tunneling junctions has been found by us. Based on this mechanism, we designed and fabricated a 2 x 2 bit Spin Tunneling Random Access Memory (STram). These junctions provide an excellent means of storing a binary data in the hard components, and sensing its remanent state by switching the soft component in such a way that the magnetic state of the hard component remains unaltered.

SnSe, Sn[Se.sub.2] and [Sn.sub.2][Se.sub.3] alloys are studied for exploring their suitability as new phase change alloys for electronic memory applications. The studies have shown that Sn[Se.sub.2] is a good candidate for phase change memories, as it can minimize the reset current of phase change random access memory (PCRAM) devices.

Random-access memory switches are fabricated by using 70 nm thick spun films of nonperipherally octahexyl substituted lead phthalocyanine (PbPc) molecules sandwiched between indium tin oxide (ITO) substrates and vacuum-deposited aluminum (Al) top electrodes. The bistable electrical switching effects are attributed to the existence of the depletion layer at the ITO/PbPc and exponential distribution in energy of traps in nonactive region of PbPc films.

The magnetoresistance (MR) contribution is examined in a ring-shaped ferromagnetic structure with local current and voltage contacts. The results have provided a convenient way for interpreting the magnetization reversal process in ferromagnetic ring structures and magnetic random access memory design.

The dynamic switching in magnetic access memory (MRAM) and its dependence on thermal effects due to a finite temperature are studied. The thermal fluctuations are shown to affect the switching behavior, the reliability and the writing speed of MRAM devices.

The interlayer coupling of CoFeB-based synthetic antiferromagnets (SyAFs), modulated by the ion-beam assisted deposition (IBAD) is investigated under different assisted deposition voltage. These methods have provided a convenient method to increase the magnetic coupling of SyAFs, which is useful for the magnetic tunnel junction fabrication and magnetoresistive random access memory development.

A simple and fast method for sensing four states from a single Pseudo-Spin Valve GMR device is presented. Four state sensing shows promise of doubling the potential bit density of Magnetic Random Access Memory (MRAM) and related devices. A new two step method to detect the GMR bit information has been developed here that is simple to implement and which easily allows for compensation of rapid self-heating effects. Index terms--GMR, MRAM, sense amplifier, four-state logic, comparator.