Search

Deep reactive ion etching (DRIE) is an enabling technology for three dimensional (3D) integration of planar integrated circuits. This work focuses on various challenges associated with deep reactive ion etching technology for realizing through silicon interconnection for 3D Microsystems application. In the first part of the thesis, stress simulation studies were done on TSV structures of various via geometries and shapes to determine the regions of high stress due to CTE mismatch. It was determined that the top and bottom of the vias and the surrounding materials experience maximum mechanical stress. It was also found that the stress is concentrated in the sharp peaks and valleys of the scallops formed by Bosch etch process. A test vehicle was designed and fabricated by copper damascene process with various geometries and barrier structures to experimentally study the effect of sidewall scallops on electrical leakage between adjacent TSV structures. It was shown that the leakage current can be reduced by about nearly 3 orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall for the initial few microns of the depth of the via by using a non-Bosch etch process. This study has shown that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, for vertical TSV etch application by tailoring a short first etch step with smooth sidewall. DOCTOR OF PHILOSOPHY (EEE)

A series of images, ideas, emotions, and sensations that happen involuntarily in the mind at the time of sleep are known as dreams. A definite understanding of the content and purpose of dreams is not yet established. They have frequently been a subject of scientific assumption and a focus of philosophical and religious interest.

A novel two step etch process using the Bosch-etch mechanism to prevent notching on an SOI wafer is presented. The first etch step is used to attain the maximum etch depth with high etch rate and stop before the buried oxide (BOX). Followed by the second etch step with lower etch rate and tuned to soft land on the BOX to etch the remaining depth. In addition to that it is tailored to also provide a tapered etch profile which is beneficial in reducing the notch if over etching occurs.

Portable electronic products demand multifunctional module comprising of digital, radio frequency and memory functions. Through silicon via (TSV) technology provides a means of implementing complex, multifunctional integration with a higher packing density for a system in package. A 3-D silicon module with TSV has been developed in this paper. Thermo-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the barrier copper via is exposed by the backgrinding process. A two-stack silicon module is developed and module fabrication details are given in this paper. The module reliability has been evaluated under temperature cycling (-40/125°C ) and drop test.

A wafer-level vacuum package with getters deposited on the cap wafer is developed for an accelerometer device. An accelerometer wafer and cap wafer is bonded together in a vacuum of 1 mtorr and is characterized using a micro-electro-mechanical systems (MEMS) motion analyzer (MMA). Vacuum inside the package is measured indirectly by measuring the Q-factor response of the accelerometer structure inside the package. The obtained results indicated that there is variation from the center to the edge of the wafer. This may be due to difference in the outgassing of the package. Different reliability tests on the wafer-level package showed the package is robust to the reliability conditions. A progressive test on the Q-factor for different cycles of reliability test proved that there is no shift in the measurement value. A 3-D wafer-level package for accelerometer device is also developed to meet the requirements of vacuum packaging. Hermeticity and CV test showed no degradation in the device performance when subjected to reliability tests.

In this paper, a novel compliant chip-to-package interconnect, planar microspring, is presented in terms of design consideration, wafer-level fabrication process and mechanical characterization. Several spring designs have been evaluated, and results indicate that a J-shaped spring design produces a combination of high 3D compliances and acceptable electrical parasitics. Further, numerical analyses on the J -shaped microspring interconnect examined the dependence of mechanical and electrical performance upon geometry parameters. A wafer-level fabrication flow combining complementary metal oxide semiconductor (CMOS) back-end-of-line (BEOL) process and 3-D surface micromachining technique has been successfully implemented to create planar microspring interconnect prototypes with a fine pitch (100 mum). The mechanical robustness of the prototype interconnects have been evaluated by nanoindentation. Finally, high-frequency electrical simulation suggested that the interconnect application can be extended up to ~35 GHz without significant power loss.

Stacking of many functional chips in a 3-D stack package leads to high heat dissipation. Therefore, a new platform technology is required to assemble chips vertically and remove the heat effectively. A 3-D stacked package with silicon interposers was developed to integrate one ASIC and two memory chips in a package. Electrical connections in the silicon interposer were formed by through silicon via. Silicon interposer has much high thermal conductivity than organic interposer, therefore the package thermal resistance is lower. Thermal performances of the 3-D package were analyzed and thermal enhancements like thermal via, thermal bridging were evaluated. The designed package showed 5 times lesser thermal resistance compared to a similar package with organic substrate. An additional silicon heat spreader was designed and attached to the package for high power application. Thermal analysis was performed to optimize package thermal performances and experimental validation was carried out. The designed 3-D stack package is suitable for 20 W application.

A novel dual-etch process technology has been developed for the tapering of deep silicon vias which can be used in the fabrication of through-silicon interconnected silicon carriers for 3D system in packaging application. The process consists of two etching steps viz. an anisotropic etch process followed by a global isotropic etch process which causes the vias profile to taper. The 1st etching step is designed to provide high etch rate and throughput while the 2nd etch step is designed to control the taper angle of the via. It has been shown that through this approach of partitioning the via formation process into an anisotropic etch and an isotropic etch process, it is possible to maintain high overall etch rates without compromising on the final via profile and throughput. The via profile achieved has been extensively characterized with respect wide range of critical process parameters and via geometries. It has been demonstrated that regardless of the choice of via formation method, it is feasible to achieve a controllable via taper to realize a void-free copper via-filling by electroplating process.

This paper addresses fatigue and bridging issues by numerical analysis for an ultra-fine-pitch flip-chip interconnect that consists of multiple copper columns (MCC) and a solder joint. First, the processing flow is briefly presented, which enables prototyping of high-aspect-ratio (~6) copper columns, and hence, enhanced thermomechanical reliability of the interconnects. A public software, Surface Evolver (SE), has been used through this work to predict the solder joint geometry evolution. By integrating SE solder joint shape modeling, stress/strain analysis within ANSYS, and design of experiment (DoE) techniques as well, detailed numerical analysis has been conducted on the solder joint fatigue response to various factors such as the Cu-Solder wetting angle, loading direction, and solder geometry parameters. Finally, by applying the DoE techniques and the most updated features of SE, bridging risks of this interconnect with a fine pitch of 40mum is investigated, in which critical solder volume is calculated as a function of the interconnect geometry parameters. Based on these results, a solid basis for the design and processing of this advanced flip-chip interconnect has been established

This paper presents modeling and simulation results of a modified copper-column-based flip-chip interconnect with ultrafine pitch for wafer-level packaging, and the process and prototyping procedure are described as well. This interconnect consists of multiple copper columns which are electrically in parallel and supporting a solder bump. A simple analytical model has been developed for correlation between the interconnect geometry and the thermal fatigue life. In comparison to the conventional single-copper-column (SCC) interconnects, numerical analysis reveals that the multi-copper-column (MCC) interconnect features enhanced compliances and, hence, higher thermomechanical reliability, while the associated electrical parasitics (R, L, and C) at dc and moderate frequencies are still kept low. Parametric studies reveal the effects of geometric parameters of MCC interconnects on both compliances and electrical parasitics, which in turn facilitate design optimization for best performance. By using coplanar waveguides (CPWs) as feed lines on both chip and package substrate, a high-frequency (up to 40 GHz) S-parameter analysis is conducted to investigate the transmission characteristics of the MCC interconnects within various scenarios which combines various interconnect pitches and common chip and package substrates. An equivalent lumped circuit model is proposed and the circuit parameters (R, L, C, and G) are obtained throughout a broad frequency range. Good agreement is achieved for the transmission characteristics between the equivalent lumped circuit model and direct simulation results.

A low temperature resist trimming process with low trimming rate and good uniformity was developed. Wafer chuck temperature in the ashing chamber was adjusted to be 6 °C to achieve low trimming rate and improve process uniformity. Low power oxygen and argon plasma was used for ashing the resist. Resist lines (0.5 μm wide) patterned with a g-line stepper was trimmed down to sub-100 nm widths. The trimming rate was found to be independent of the initial line width and trimming time. A 0.6 μm CMOS process flow with LOCOS and nitride spacer was suitably modified incorporating resist trimming to fabricate NMOSFETs with gate length as small as 95 nm. Since most polymer-based photoresists can be etched in oxygen plasma, the basic technique could be extended to supplement other lithographic processes for channel length scaling.

International audience; ISVLSI 2014 explores emerging trends, novel ideas and concepts in the area of VLSI. The Symposium covers a wide range of topics from emerging technologies to design methods to system level design of VLSI circuits and systems. The topics also include future design methodologies and VLSI CAD to support these technologies. For the past two decades, the conference has been a unique forum for promoting visionary approaches to VLSI design process and an esteemed venue for presenting multidisciplinary research. The Symposium brings together leading scientists and researchers from academia and industry. The papers from this symposium have been published as special issues of top archival journals. These traditions will be continued in 2014. The symposium proceedings will be published by the IEEE Computer Society Press.

This paper presents the development of a low temperature silicon nitride deposition process using plasma enhanced chemical vapor deposition (PECVD) system. The nitride films showed low stresses ranging from compressive to tensile and very low etch rates in the buffered oxide etch (BOE) solution. These nitride films can be used as MEMS structure materials where suspended structures are involved. In this work, individual process parameters such as SiH 4 /H 2 /N 2 gas flows, chamber pressures, temperatures and HF powers that related to the nitride film stress and etch rate in BOE solution are also investigated.

In this paper, a method of fabricating radio opaque silicon micro needles for tissue labeling applications is reported. Cylindrical shaped micro needles ranging from 7 × 7 to 11 × 11 arrays with a pitch varying from 60 µm to 100µm are fabricated in silicon using a three step mask process. A backside cavity is generated under DRIE for filling the radiopaque material. Barium sulphate is filled in and a biocompatible sealing is provided to hold the radiopaque material inside. The fabricated needles provide a better contrast enhancement under x-ray imaging.

This paper presents our development work to achieve high aspect ratio void-free polymer via filling with various types of organic materials for potential application in 3D wafer level packaging. This study focuses on the development of via filling process using the conventional spin-coating and curing process. Thermoplastic polymers have been selected for this evaluation due to its ability to reflow and fill gaps easily. Test wafers with circular via patterns with diameters from 1–70 µm with aspect ratios from 1–10 have been evaluated. The various challenges to achieving void-free via filling have been presented and it has been demonstrated that a void-free filling is feasible for vias with aspect ratio of 1–8.

A detailed study to perform low temperature (< 200°C) PECVD TEOS-oxide deposition process with very low mechanical stress and good conformal deposition on high aspect ratio features (10∶1) was done. Individual conditions that affect the oxide stress and deposition rate such as TEOS & O2 flow rate, HF/LF power, pressure and temperature are investigated. The optimal conditions found are used to then deposited into trenches and further fine tuned to give excellent step coverage for high aspect ratio features.