199 results on '"Ravi, Srivaths"'
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2. A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing
3. Site-to-Site Variation in Analog Multisite Testing: A Survey on Its Detection and Correction
4. Hardware Accelerated Power Estimation
5. Security Standards for Embedded Devices and Systems
6. Cross-Correlation Approach to Detecting Issue Test Sites in Massive Parallel Testing
7. Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing
8. A Framework for Extensible Processor Based MPSoC Design
9. POS1 - Graph Theory Approach for Multi-site ATE Board Parameter Extraction
10. Graph Theory Approach for Multi-site ATE Board Parameter Extraction
11. The Least-Squares Approach to Systematic Error Identification and Calibration in Semiconductor Multisite Testing
12. Emerging Challenges in Designing Secure Mobile Appliances
13. Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
14. Massive Multisite Variability-Aware Die Distribution Estimation for Analog/Mixed-Signal Circuits Test Validation
15. An Ordinal Optimization-Based Approach To Die Distribution Estimation For Massive Multi-site Testing Validation: A Case Study
16. Detection of Site to Site Variations from Volume Measurement Data in Multi-site Semiconductor Testing
17. A synthesis methodology for hybrid custom instruction and coprocessor generation for extensible processors
18. Automated energy/performance macromodeling of embedded software
19. Test-volume reduction in systems-on-a-chip using heterogeneous and multilevel compression techniques
20. RTL-aware cycle-accurate functional power estimation
21. Use of computation-unit integrated memories in high-level synthesis
22. Application-specific heterogeneous multiprocessor synthesis using extensible processors
23. Satisfiability-based test generation for nonseparable RTL controller-datapath circuits
24. Generation of distributed logic-memory architectures through high-level synthesis
25. A hybrid energy-estimation technique for extensible processors
26. Custom-instruction synthesis for extensible-processor platforms
27. Test synthesis of systems-on-a-chip
28. High-level test compaction techniques
29. Fault-diagnosis-based technique for establishing RTL and gate-level correspondences
30. Quantile – Quantile Fitting Approach to Detect Site to Site Variations in Massive Multi-site Testing
31. Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits
32. Detection of Site to Site Variations From Volume Measurement Data in Multisite Semiconductor Testing.
33. Demystifying automotive safety and security for semiconductor developer
34. Foreword
35. Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems
36. Methodology for Early RTL Testability and Coverage Analysis and Its Application to Industrial Designs
37. Systematic software-based self-test for pipelined processors
38. Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices
39. Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test
40. Methodology for early and accurate test power estimation at RTL
41. A generic low power scan chain wrapper for designs using scan compression
42. Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures
43. Power Analysis and Reduction Techniques for Transition Fault Testing
44. A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips
45. Low Power Test for Nanometer System-on-Chips (SoCs)
46. Variability-Tolerant Register-Transfer Level Synthesis
47. Energy-optimizing source code transformations for operating system-driven embedded software
48. A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors
49. Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis
50. Hybrid Simulation for Energy Estimation of Embedded Software
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