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199 results on '"Ravi, Srivaths"'

4. Hardware Accelerated Power Estimation

Author

Coburn, Joel, Ravi, Srivaths, and Raghunathan, Anand

Subjects
Computer Science - Hardware Architecture
Abstract

In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the observation that the functions necessary for power estimation (power model evaluation, aggregation, etc.) can be implemented as hardware circuits. Therefore, we can enhance any given design with "power estimation hardware", map it to a prototyping platform, and exercise it with any given test stimuli to obtain power consumption estimates. Our empirical studies with industrial designs reveal that power emulation can achieve significant speedups (10X to 500X) over state-of-the-art commercial register-transfer level (RTL) power estimation tools., Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

Published
2007

9. POS1 - Graph Theory Approach for Multi-site ATE Board Parameter Extraction

Author

Steenhoek, Abraham, Farayola, Praise O., Bruce, Isaac, Chaganti, Shravan, Sheikh, Abalhassan, Ravi, Srivaths, and Chen, Degang

Subjects
Microelectronics, Integrated circuits, Microelectrònica, Spintronics, Graph Theory, Site to Site (s2s) Variations, Circuits integrats, Espintrònica, Multisite Testing(MST), Automatic Test Equipment (ATE), Test Board, Enginyeria electrònica::Microelectrònica [Àrees temàtiques de la UPC]
Abstract

This paper describes a low-cost technique for extracting parameters of interest for test boards used in multisite automatic test equipment (ATE). In the proposed approach, physical elements and nets on the PCB are represented as a graph with nodes and edges. Graph traversal algorithms are then used to extract data about the connections between specific components on each test site. This approach automates the previously slow and manual process of generating the topology files necessary to extract board parameters. The proposed method is implemented on a multisite test board, and results are presented.

Published
2022

18. Automated energy/performance macromodeling of embedded software

Author

Muttreja, Anish, Raghunathan, Anand, Ravi, Srivaths, and Jha, Niraj K.

Subjects
Embedded system, System on a chip, Computer programming, Genetic algorithms -- Analysis, Embedded systems -- Design and construction, Computer programming -- Methods, Estimation theory -- Analysis
Published
2007

20. RTL-aware cycle-accurate functional power estimation

Author

Lin Zhong, Ravi, Srivaths, Raghunathan, Anand, and Jha, Niraj K.

Subjects
Circuit designer, Integrated circuit design, Embedded system, System on a chip, Computer-generated environments -- Analysis, Computer simulation -- Analysis, Circuit design -- Analysis, Embedded systems -- Design and construction
Published
2006

21. Use of computation-unit integrated memories in high-level synthesis

Author

Chao Huang, Ravi, Srivaths, Raghunathan, Anand, and Jha, Niraj K.

Subjects
Application-specific integrated circuit, Custom IC, Semiconductor memory, Application-specific integrated circuits -- Design and construction, Custom integrated circuits -- Design and construction, Memory (Computers) -- Design and construction, Electric circuit analysis
Published
2006

22. Application-specific heterogeneous multiprocessor synthesis using extensible processors

Author

Fei Sun, Ravi, Srivaths, Raghunathan, Anand, and Jha, Niraj K.

Subjects
Application-specific integrated circuit, Custom IC, Embedded system, System on a chip, Application-specific integrated circuits -- Design and construction, Custom integrated circuits -- Design and construction, Multiprocessors -- Design and construction, Embedded systems -- Design and construction
Published
2006

24. Generation of distributed logic-memory architectures through high-level synthesis

Author

Chao Huang, Ravi, Srivaths, Raghunathan, Anand, and Jha, Niraj K

Subjects
Storage capacity, Distributed processing (Computers), Memory compaction -- Methods, Memory management -- Methods, Memory mapping -- Methods, Memory partitioning -- Methods, Memory protection -- Methods, Memory refresh (Computers) -- Methods, Distributed processing (Computers) -- Methods, Scheduling (Management) -- Analysis
Published
2005

25. A hybrid energy-estimation technique for extensible processors

Author

Yunsi Fei, Ravi, Srivaths, Raghunathan, Anand, and Jha, Niraj K.

Subjects
Embedded system, System on a chip, Standard IC, Microprocessor, Microprocessor upgrade, Semiconductor chips -- Analysis, Embedded systems -- Analysis, Integrated circuits -- Analysis, Microprocessors -- Analysis
Published
2004

27. Test synthesis of systems-on-a-chip

Author

Ravi, Srivaths and Jha, Niraj K.

Subjects
Standard IC, Microprocessor, Microprocessor upgrade, Integrated circuits -- Research, Integrated circuits -- Design and construction, Semiconductor chips, Microprocessors -- Research
Published
2002

28. High-level test compaction techniques

Author

Ravi, Srivaths, Lakshminarayana, Ganesh, and Jha, Niraj K.

Subjects
Integrated circuit design, Automatic testing equipment -- Research, Testing and measuring equipment industry -- Research, Integrated circuits -- Research, Semiconductor industry -- Research
Published
2002

32. Detection of Site to Site Variations From Volume Measurement Data in Multisite Semiconductor Testing.

Author

Farayola, Praise O., Chaganti, Shravan K., Obaidi, Abdullah O., Sheikh, Abalhassan, Ravi, Srivaths, and Chen, Degang

Subjects
VOLUME measurements, MIXED signal circuits, STATISTICAL learning, INTEGRATED circuits, SEMICONDUCTORS
Abstract

The rising analog content in mixed-signal integrated circuits (ICs) is driving an increased need for measurement of analog parametric specifications during manufacturing test, thereby significantly increasing overall chip cost. Multisite (parallel) measurement alleviates this issue by measuring multiple chips at the same time, hence massively increasing throughput and reducing measurement time per chip. For successful multisite test and measurement, product and test engineers have to design multisite boards that can ensure robust measurement and test quality for each site. However, as the number of sites increases, variations in site to site behavior are often seen, leading to degradation of test results at some sites. These variations result from various artifacts such as nonhomogenous layout and routing, compromises in component placement, etc. Very often, methods to detect board and site anomalies are ad hoc, leading to a time-consuming and expensive diagnosis cycle. Therefore, there is a need for a cost-effective approach to investigate and identify SSV from measurement data. This work proposes an automated technique that leverages advanced statistical learning methods to pronounce and detect SSV not always visible to human inspections of measurement data. Specifically, we contribute the concept of using domain transformation that converts measurement data in the specification value space to a statistical parameter space, allowing for robust automatic detectability of SSV. Robustness and accuracy of the method are confirmed after application to real-world industrial and simulated measurement data. [ABSTRACT FROM AUTHOR]

Published
2021
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34. Foreword

Author

Makris, Yiorgos, primary, Ravi, Srivaths, additional, and Majumdar, Amit, additional

Published
2017
Full Text
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37. Systematic software-based self-test for pipelined processors

Author

Psarakis, Mihalis Gizopoulos, Dimitris Hatzimihail, Miltiadis and Paschalis, Antonis Raghunathan, Anand Ravi, Srivaths

Subjects
Hardware_PERFORMANCEANDRELIABILITY
Abstract

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in Systems-on-Chip (SoCs). By moving test related functions from external resources to the SoC’s interior, in the form of test programs that the on-chip processor executes, SBST eliminates the need for high-cost testers, and enables high-quality at-speed testing. Thus far, SBST approaches have focused almost exclusively on the functional (directly programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are insufficient to test the pipeline logic, resulting in a significant loss of fault coverage. We further identify the testability hotspots in the pipeline logic. Finally, we develop a systematic SBST methodology that enhances existing SBST programs to comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology), and can reuse the test development effort behind existing SBST programs. We applied the methodology to two complex, fully pipelined processors. Results show that our methodology provides fault coverage improvements of up to 15% (12% on average) for the entire processor, and fault coverage improvements of 22% for the pipeline logic, compared to a conventional SBST approach.

Published
2006

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