Search

Resistive random access memory (ReRAM) holds promise for building computing-in-memory (CIM) architectures to execute machine learning (ML) applications. However, existing ReRAM technology faces challenges such as cell and cycle variability, read-disturb and limited endurance, necessitating improvements in devices, algorithms and applications. Understanding the behaviour of ReRAM technologies is crucial for advancement. Existing platforms can either only characterize single cells and do not support CIM operations, or lack a comprehensive software stack for simple system integration. This article introduces NeuroBreakoutBoard (NBB), a versatile, integrable and portable instrumentation platform for ReRAM crossbars. The platform features a software stack enabling experiments via Python from a host PC. In a case study, we demonstrate the capabilities of NBB by conducting diverse experiments on TiN/Ti/HfO2/TiN cells. Our results show that NBB can characterize individual cells and perform CIM operations with a relative measurement error below 2%. This article is part of the theme issue 'Emerging technologies for future secure computing platforms'. [ABSTRACT FROM AUTHOR]

Oxidation of 2D layered materials has proven advantageous in creating oxide/2D material heterostructures, opening the door for a new paradigm of low‐power electronic devices. Gallium (II) sulfide (β‐GaS), a hexagonal phase group III monochalcogenide, is a wide bandgap semiconductor with a bandgap exceeding 3 eV in single and few‐layer form. Its oxide, gallium oxide (Ga2O3), combines a large bandgap (4.4–5.3 eV) with a high dielectric constant (≈10). Despite the technological potential of both materials, controlled oxidation of atomically‐thin β‐GaS remains under‐explored. This study focuses on the controlled oxidation of β‐GaS using oxygen plasma treatment, addressing a significant gap in existing research. The results demonstrate the ability to form ultrathin native oxide (GaSxOy), 4 nm in thickness, upon exposure to 10 W of O2, resulting in a GaSxOy/GaS heterostructure where the GaS layer beneath remains intact. By integrating such structures between metal electrodes and applying electric stresses as voltage ramps or pulses, their use for resistive random‐access memory (ReRAM) is investigated. The ultrathin nature of the produced oxide enables low operation power with energy use as low as 0.22 nJ per operation while maintaining endurance and retention of 350 cycles and 104 s, respectively. These results show the significant potential of the oxidation‐based GaSxOy/GaS heterostructure for electronic applications and, in particular, low‐power memory devices. [ABSTRACT FROM AUTHOR]

This paper presents the results of experimental studies of the influence of high-frequency magnetron sputtering power on the structural and electrophysical properties of nanocrystalline ZnO films. It is shown that at a magnetron sputtering power of 75 W in an argon atmosphere at room temperature, ZnO films have a relatively smooth surface and a uniform nanocrystalline structure. Based on the results obtained, the formation and study of resistive switching of transparent ITO/ZnO/ITO memristor structures as well as a crossbar array based on them were performed. It is demonstrated that memristor structures based on ZnO films obtained at a magnetron sputtering power of 75 W exhibit stable resistive switching for 1000 cycles between high resistance states (HRS = 537.4 ± 26.7 Ω) and low resistance states (LRS = 291.4 ± 38.5 Ω), while the resistance ratio in HRS/LRS is ~1.8. On the basis of the experimental findings, we carried out mathematical modeling of the resistive switching of this structure, and it demonstrated that the regions with an increase in the electric field strength along the edge of the upper electrode become the main sources of oxygen vacancy generation in ZnO film. A crossbar array of 16 transparent ITO/ZnO/ITO memristor structures was also fabricated, demonstrating 20,000 resistive switching cycles between LRS = 13.8 ± 1.4 kΩ and HRS = 34.8 ± 2.6 kΩ for all devices, with a resistance ratio of HRS/LRS of ~2.5. The obtained results can be used in the development of technological processes for the manufacturing of transparent memristor crossbars for neuromorphic structures of machine vision, robotics, and artificial intelligence systems. [ABSTRACT FROM AUTHOR]

Strain engineering provides an attractive approach to enhance device performance by modulating the intrinsic electrical properties of materials. This is especially applicable to 2D materials, which exhibit high sensitivity to mechanical stress. However, conventional methods, such as using polymer substrates, to apply strain have limitations in that the strain is temporary and global. Here, we introduce a novel approach to induce permanent localized strain by fabricating a stressor on SiO2/Si substrates using fiber laser irradiation, thereby enabling precise control of the surface topography. MoS2 is transferred onto this stressor, which results in the application of ~0.8% tensile strain. To assess the impact of the internal strain on the operation of ReRAM devices, the flat-MoS2-based and the strained-MoS2-based devices are compared. Both devices demonstrate forming-free, bipolar, and non-volatile switching characteristics. The strained devices exhibit a 30% reduction in the operating voltage, which can be attributed to bandgap narrowing and enhanced carrier mobility. Furthermore, the strained devices exhibit nearly a two-fold improvement in endurance, presumably because of the enhanced stability from lattice release effect. These results emphasize the potential of strain engineering for advancing the performance and durability of next-generation memory devices. [ABSTRACT FROM AUTHOR]

Most existing architectural studies on ReRAM-based processing-in-memory (PIM) DNN accelerators assume that all weights of the DNN can be mapped to the crossbar at once. However, these studies are over-idealized. ReRAM crossbar resources for calculation are limited because of technological limitations, so multiple weight mapping procedures are required during the inference process. In this article, we propose a static scheduling framework which generates the mapping between DNN weights and ReRAM cells with minimum runtime weight programming cost. We first build a ReRAM crossbar programming latency model by simultaneously considering the DNN weight patterns, ReRAM programming operations, and PIM architecture characteristics. Then, the model is used in the searching process to obtain an optimized weight-to-OU mapping table with minimum online programming latency. Finally, an OU scheduler is used to coordinate the activation sequences of OUs in the crossbars to perform the inference computation correctly. Evaluation results show the proposed framework significantly reduces the weight programming overhead and the overall inference latency for various DNN models with different input datasets. [ABSTRACT FROM AUTHOR]

Modern recommendation systems are widely used in modern data centers. The random and sparse embedding lookup operations are the main performance bottleneck for processing recommendation systems on traditional platforms as they induce abundant data movements between computing units and memory. ReRAM-based processing-in-memory (PIM) can resolve this problem by processing embedding vectors where they are stored. However, the embedding table can easily exceed the capacity limit of a monolithic ReRAM-based PIM chip, which induces off-chip accesses that may offset the PIM profits. Therefore, we deploy the decomposed model on-chip and leverage the high computing efficiency of ReRAM to compensate for the decompression performance loss. In this paper, we propose ARCHER, a ReRAM-based PIM architecture that implements fully on-chip recommendations under resource constraints. First, we make a full analysis of the computation pattern and access pattern on the decomposed table. Based on the computation pattern, we unify the operations of each layer of the decomposed model in multiply-and-accumulate operations. Based on the access observation, we propose a hierarchical mapping schema and a specialized hardware design to maximize resource utilization. Under the unified computation and mapping strategy, we can coordinate the inter-processing elements pipeline. The evaluation shows that ARCHER outperforms the state-of-the-art GPU-based DLRM system, the state-of-the-art near-memory processing recommendation system RecNMP, and the ReRAM-based recommendation accelerator REREC by 15.79×, 2.21×, and 1.21× in terms of performance and 56.06×, 6.45×, and 1.71× in terms of energy savings, respectively. [ABSTRACT FROM AUTHOR]

A nonlinear system, exhibiting a unique asymptotic behaviour, while being continuously subject to a stimulus from a certain class, is said to suffer from fading memory. This interesting phenomenon was first uncovered in a non-volatile tantalum oxide-based memristor from Hewlett Packard Labs back in 2016 out of a deep numerical investigation of a predictive mathematical description, known as the Strachan model, later corroborated by experimental validation. It was then found out that fading memory is ubiquitous in non-volatile resistance switching memories. A nonlinear system may however also exhibit a local form of fading memory, in case, under an excitation from a given family, it may approach one of a number of distinct attractors, depending upon the initial condition. A recent bifurcation study of the Strachan model revealed how, under specific train stimuli, composed of two square pulses of opposite polarity per cycle, the simplest form of local fading memory affects the transient dynamics of the aforementioned Resistive Random Access Memory cell, which, would asymptotically act as a bistable oscillator. In this manuscript we propose an analytical methodology, based on the application of analysis tools from Nonlinear System Theory to the Strachan model, to craft the properties of a generalised pulse train stimulus in such a way to induce the emergence of complex local fading memory effects in the nano-device, which would consequently display an interesting tuneable multistable oscillatory response, around desired resistance states. The last part of the manuscript discusses a case study, shedding light on a potential application of the local history erase effects, induced in the device via pulse train stimulation, for compensating the unwanted yet unavoidable drifts in its resistance state under power off conditions. [ABSTRACT FROM AUTHOR]

Abstract Oxidation of 2D layered materials has proven advantageous in creating oxide/2D material heterostructures, opening the door for a new paradigm of low‐power electronic devices. Gallium (II) sulfide (β‐GaS), a hexagonal phase group III monochalcogenide, is a wide bandgap semiconductor with a bandgap exceeding 3 eV in single and few‐layer form. Its oxide, gallium oxide (Ga2O3), combines a large bandgap (4.4–5.3 eV) with a high dielectric constant (≈10). Despite the technological potential of both materials, controlled oxidation of atomically‐thin β‐GaS remains under‐explored. This study focuses on the controlled oxidation of β‐GaS using oxygen plasma treatment, addressing a significant gap in existing research. The results demonstrate the ability to form ultrathin native oxide (GaSxOy), 4 nm in thickness, upon exposure to 10 W of O2, resulting in a GaSxOy/GaS heterostructure where the GaS layer beneath remains intact. By integrating such structures between metal electrodes and applying electric stresses as voltage ramps or pulses, their use for resistive random‐access memory (ReRAM) is investigated. The ultrathin nature of the produced oxide enables low operation power with energy use as low as 0.22 nJ per operation while maintaining endurance and retention of 350 cycles and 104 s, respectively. These results show the significant potential of the oxidation‐based GaSxOy/GaS heterostructure for electronic applications and, in particular, low‐power memory devices.

Fading memory is the capability of a physical system to approach a unique asymptotic behaviour, irrespective of the initial conditions, when stimulated by an input from a certain class. Standard stimuli from the AC periodic class typically induce fading memory effects in non-volatile memristors, as uncovered for the first time back in 2016. Very recently, a deep investigation of resistance switching phenomena in a TaOx resistive random access memory cell revealed the capability of the nano-device to exhibit one of two possible oscillatory behaviours, depending upon the initial condition, when subject to a particular periodic excitation. This interesting finding was, however, left unexplained. Bistability is the simplest form of local fading memory. In a system, endowed with local fading memory under a given stimulus, the initial condition does not affect the long-term behaviour of the state as long as it is drawn from the basin of attraction of either of the distinct coexisting state-space attractors (two limit cycles for the periodically forced memristor acting as a bistable oscillator). Here, the history of the system, encoded in the initial condition, is, thus, erasable only locally through ad hoc stimulation. Motivated by the discovery of local history erase effects in our resistive random access memory cell, this study applies a powerful system-theoretic tool, enabling the analysis of the response of first-order systems to square pulse train-based periodic stimuli, known as the time-average state dynamic route, to an accurate physics-based mathematical model, earlier fitted to the nano-device, to determine a strategy for specifying the parameters of an excitation signal, consisting of the sequence of two square pulses of opposite polarity per period so as to induce various forms of monostability or multistability in the non-volatile memristor. In particular, as an absolute novelty in the literature, experimental measurements validate the theoretical prediction on the capability of the device to operate as one of two distinct oscillators, depending upon the initial condition, under a specific pulse train excitation signal. The coexistence of multiple oscillatory operating modes in the periodically forced resistive random access memory cell, an example par excellence of their unique nonlinear dynamics, may inspire the development and circuit implementation of novel sensing and mem-computing paradigms. [ABSTRACT FROM AUTHOR]

We studied the phase change and resistive switching characteristics of copper oxide (Cu x O) films through post-thermal annealing. This investigation aimed to assess the material's potential for a variety of electrical devices, exploring its versatility in electronic applications. The Cu x O films deposited by RF magnetron sputtering were annealed at 300, 500, and 700 °C in ambient air for 4 min by rapid thermal annealing (RTA) method, and then it was confirmed that the structural phase change from Cu2O to CuO occurred with increasing annealing temperature. Resistive random-access memory (ReRAM) devices with Au/Cu x O/p+-Si structures were fabricated, and the ReRAM properties appeared in CuO-based devices, while Cu2O ReRAM devices did not exhibit resistive switching behavior. The CuO ReRAM device annealed at 500 °C showed the best properties, with a on/off ratio of 8 × 102, good switching endurance of ∼100 cycles, data retention for 104 s, and stable uniformity in the cumulative probability distribution. This characteristic change could be explained by the difference in the grain size and density of defects between the Cu2O and CuO films. These results demonstrate that superior and stable resistive switching properties of RF-sputtered Cu x O films can be obtained by low-temperature RTA. [ABSTRACT FROM AUTHOR]

The objective of this work is to present a comparison of the switching properties in Resistive Random-Access-Memory between two different switching layer devices through the capacitance measurements. The analysis was carried out in two devices with different insulating layers, one composed of H-plasma-treated ${\mathrm { HfO}}_{2}$ and another with a stoichiometric HfO2. The device with a higher quantity of oxygen vacancy-related defects in the insulator (HfO2 w/trt) presents a wider spread of the capacitance with the application of a range of varying pulse widths. An increase in the capacitance from 3.904 to 3.917 pF/ $\mu $ m2 was observed for the same device when it was subjected to a $144~\mu $ s pulse width, demonstrating a conductance quantization required for the application in in-memory computing systems. Also, the dielectric constant modulates due to the migration of oxygen atoms inside the device’s insulator.

The high speed, scalability, and parallelism offered by ReRAM crossbar arrays foster the development of ReRAM-based next-generation AI accelerators. At the same time, the sensitivity of ReRAM to temperature variations decreases $\text{R}_{ON}/\text{R}_{OFF}$ ratio and negatively affects the achieved accuracy and reliability of the hardware. Various works on temperature-aware optimization and remapping in ReRAM crossbar arrays reported up to 58% improvement in accuracy and $2.39\times $ ReRAM lifetime enhancement. This paper classifies the challenges caused by thermal heat, starting from constraints in ReRAM cells’ dimensions and characteristics to their placement in the architecture. In addition, it reviews the available solutions designed to mitigate the impact of these challenges, including emerging temperature-resilient Deep Neural Network (DNN) training methods. Our work also provides a summary of the techniques and their advantages and limitations.

Fading memory is the capability of a physical system to approach a unique asymptotic behaviour, irrespective of the initial conditions, when stimulated by an input from a certain class. Standard stimuli from the AC periodic class typically induce fading memory effects in non-volatile memristors, as uncovered for the first time back in 2016. Very recently, a deep investigation of resistance switching phenomena in a TaOx resistive random access memory cell revealed the capability of the nano-device to exhibit one of two possible oscillatory behaviours, depending upon the initial condition, when subject to a particular periodic excitation. This interesting finding was, however, left unexplained. Bistability is the simplest form of local fading memory. In a system, endowed with local fading memory under a given stimulus, the initial condition does not affect the long-term behaviour of the state as long as it is drawn from the basin of attraction of either of the distinct coexisting state-space attractors (two limit cycles for the periodically forced memristor acting as a bistable oscillator). Here, the history of the system, encoded in the initial condition, is, thus, erasable only locally through ad hoc stimulation. Motivated by the discovery of local history erase effects in our resistive random access memory cell, this study applies a powerful system-theoretic tool, enabling the analysis of the response of first-order systems to square pulse train-based periodic stimuli, known as the time-average state dynamic route, to an accurate physics-based mathematical model, earlier fitted to the nano-device, to determine a strategy for specifying the parameters of an excitation signal, consisting of the sequence of two square pulses of opposite polarity per period so as to induce various forms of monostability or multistability in the non-volatile memristor. In particular, as an absolute novelty in the literature, experimental measurements validate the theoretical prediction on the capability of the device to operate as one of two distinct oscillators, depending upon the initial condition, under a specific pulse train excitation signal. The coexistence of multiple oscillatory operating modes in the periodically forced resistive random access memory cell, an example par excellence of their unique non-linear dynamics, may inspire the development and circuit implementation of novel sensing and mem-computing paradigms.

Abstract Ultralow SET and RESET voltage are essential for high‐density, low‐power, and small heat dissipation nonvolatile random‐access memory (NVRAM) elements. A nanoscale polycrystalline Hf0.75Zr0.25O2 (HZO) thin films on Pt/Si substrate are fabricated and investigated for suitability for bipolar resistive switching. The device illustrates monoclinic and tetragonal/orthorhombic phases with weak ferroelectricity and robust resistive switching. Small remanent polarization (≈0.1 μC cm−2) may assist in the height reduction of barrier height and ease the electron for transport. Remarkably, the Al/HZO/Pt/Si device, consisting of thin films with 10 and 5 nm thicknesses, exhibits a switching voltage below −30 mV from a low‐resistance state (LRS) to a high‐resistance state (HRS). It shows a significant ROFF/RON ratio of 106, making it suitable for low power consumption and minimal heat dissipation devices. Moreover, the utilization of an ultrathin film (5 nm) results in an improved reduction (

Inspired by biological neuromorphic computing, artificial neural networks based on crossbar arrays of bilayer tantalum oxide memristors have shown to be promising alternatives to conventional complementary metal‐oxide‐semiconductor (CMOS) architectures. In order to understand the driving mechanism in these oxide systems, tantalum oxide films are resistively switched by conductive atomic force microscopy (C‐AFM), and subsequently imaged by kelvin probe force microscopy (KPFM) and spatially resolved time‐of‐flight secondary ion mass spectrometry (ToF‐SIMS). These workflows enable induction and analysis of the resistive switching mechanism as well as control over the resistively switched region of the film. In this work it is shown that the resistive switching mechanism is driven by both current and electric field effects. Reversible oxygen motion is enabled by applying low (<1 V) electric fields, while high electric fields generate irreversible breakdown of the material (>1 V). Fully understanding oxygen motion and electrical effects in bilayer oxide memristor systems is a fundamental step toward the adoption of memristors as a neuromorphic computing technology. [ABSTRACT FROM AUTHOR]

Atomic layer deposition (ALD) is widely utilized in the modern microelectronic industry due to its capability of depositing thin films with exceptional conformality and uniformity. The first Russian ALD system Izofaz TM 200-01 has already been successfully employed in the deposition of various materials, particularly high-k dielectrics such as aluminum oxide. This study presents the computer modeling-based investigation of the ALD process for hafnia and zirconia oxide films using the aforementioned ALD system. The growth per cycle was determined to be 1.1 Å/cycle, while the within-wafer nonuniformity was measured to be 1.2% or lower. These results are consistent with previously reported results and, more importantly, with experimental results also collected in this work, and demonstrate a high level of quality. Additionally, the electrical and physical properties of hafnia oxide films, including their potential application in ReRAM-like structures, were investigated. The storage elements based on hafnia oxide exhibited stable performance over 3 million switching cycles. Consequently, the Izofaz TM 200-01 ALD system has been proven effective in the deposition of thin films composed of hafnia and zirconia oxides. [ABSTRACT FROM AUTHOR]

Atomic layer deposition (ALD) is widely utilized in the modern microelectronic industry due to its capability of depositing thin films with exceptional conformality and uniformity. The first Russian ALD system Izofaz TM 200-01 has already been successfully employed in the deposition of various materials, particularly high-k dielectrics such as aluminum oxide. This study presents the computer modeling-based investigation of the ALD process for hafnia and zirconia oxide films using the aforementioned ALD system. The growth per cycle was determined to be 1.1 Å/cycle, while the within-wafer nonuniformity was measured to be 1.2% or lower. These results are consistent with previously reported results and, more importantly, with experimental results also collected in this work, and demonstrate a high level of quality. Additionally, the electrical and physical properties of hafnia oxide films, including their potential application in ReRAM-like structures, were investigated. The storage elements based on hafnia oxide exhibited stable performance over 3 million switching cycles. Consequently, the Izofaz TM 200-01 ALD system has been proven effective in the deposition of thin films composed of hafnia and zirconia oxides. [ABSTRACT FROM AUTHOR]

Memristive devices with valence change mechanism (VCM) show promise for neuromorphic data processing, although emulation of synaptic behavior with analog weight updates remains a challenge. Standard filamentary and area‐dependent resistive switching exhibit characteristic differences in the transition from the high to low resistance state, which is either abrupt with inherently high variability or gradual and allows quasi‐analog operation. In this study, the two switching modes are clearly correlated to differences in the microstructure and electronic structure for Pt/Al2O3/TiOx/Cr/Pt devices made from amorphous layers of 1.2 nm Al2O3 and 7 nm TiOx by atomic layer deposition. For the filamentary mode, operando spectromicroscopy experiments identify a localized region of ≈50 nm in diameter of reduced titania surrounded by crystalline rutile‐like TiO2, highlighting the importance of Joule heating for this mode. In contrast, both oxide layers remain in their amorphous state for the interfacial mode, which proves that device temperature during switching stays below 670 K, which is the TiO2 crystallization temperature. The analysis of the electronic conduction behavior confirms that the interfacial switching occurs by modulating the effective tunnel barrier width due to accumulation and depletion of oxygen vacancies at the Al2O3/TiOx interface. The results are transferable to other bilayer stacks. [ABSTRACT FROM AUTHOR]

Abstract Inspired by biological neuromorphic computing, artificial neural networks based on crossbar arrays of bilayer tantalum oxide memristors have shown to be promising alternatives to conventional complementary metal‐oxide‐semiconductor (CMOS) architectures. In order to understand the driving mechanism in these oxide systems, tantalum oxide films are resistively switched by conductive atomic force microscopy (C‐AFM), and subsequently imaged by kelvin probe force microscopy (KPFM) and spatially resolved time‐of‐flight secondary ion mass spectrometry (ToF‐SIMS). These workflows enable induction and analysis of the resistive switching mechanism as well as control over the resistively switched region of the film. In this work it is shown that the resistive switching mechanism is driven by both current and electric field effects. Reversible oxygen motion is enabled by applying low (1 V). Fully understanding oxygen motion and electrical effects in bilayer oxide memristor systems is a fundamental step toward the adoption of memristors as a neuromorphic computing technology.

Abstract Memristive devices with valence change mechanism (VCM) show promise for neuromorphic data processing, although emulation of synaptic behavior with analog weight updates remains a challenge. Standard filamentary and area‐dependent resistive switching exhibit characteristic differences in the transition from the high to low resistance state, which is either abrupt with inherently high variability or gradual and allows quasi‐analog operation. In this study, the two switching modes are clearly correlated to differences in the microstructure and electronic structure for Pt/Al2O3/TiOx/Cr/Pt devices made from amorphous layers of 1.2 nm Al2O3 and 7 nm TiOx by atomic layer deposition. For the filamentary mode, operando spectromicroscopy experiments identify a localized region of ≈50 nm in diameter of reduced titania surrounded by crystalline rutile‐like TiO2, highlighting the importance of Joule heating for this mode. In contrast, both oxide layers remain in their amorphous state for the interfacial mode, which proves that device temperature during switching stays below 670 K, which is the TiO2 crystallization temperature. The analysis of the electronic conduction behavior confirms that the interfacial switching occurs by modulating the effective tunnel barrier width due to accumulation and depletion of oxygen vacancies at the Al2O3/TiOx interface. The results are transferable to other bilayer stacks.

Dielectric breakdown (BD) is known to cause component failure in electronic devices and high‐voltage power lines over many decades. In recent years, this failure mechanism has been exploited to intentionally form nanoscale filaments in resistive random‐access‐memory (ReRAM) devices for artificial intelligence (AI). The statistical nature of this failure mechanism, known as the inverse size scaling law based on the weakest‐link theory, dictates the ever‐higher forming voltages for ReRAM devices, in turn, requiring additional peripheral transistors. This law also causes diminishing lifetimes of electronic components for future generations of very‐large‐integrated circuits (VLSI) technology. Currently, the semiconductor industry faces these scaling barriers limiting the miniaturization of both VLSI and AI hardware technology. Here, experimental evidence of a reverse area dependence is presented by introducing an innovative fabrication process with a hydrogen‐plasma‐treated layer in a bilayer HfO2 structure. Using joint order statistics rather than traditional extreme‐value statistics, a physics‐based statistical model is developed in agreement with the experimental data, thus demonstrating that there is no fundamental reason preventing this law from being reversed or altered. These findings will have a significant impact on both technology scaling and fabrication innovation for electronic and/or bioinspired nanomaterials; moreover, stimulate much research in physics, statistics, and reliability. [ABSTRACT FROM AUTHOR]

The performance stability of the resistive switching (RS) is vital for a resistive random-access memory device. Here, by inserting a thin HfAlO x layer between the InGaZnO (IGZO) layer and the bottom Pt electrode, the RS performance in amorphous IGZO memory device is significantly improved. Comparing with a typical metal-insulator-metal structure, the device with HfAlO x layer exhibits lower switching voltages, faster switching speeds, lower switching energy and lower power consumption. As well, the uniformity of switching voltage and resistance state is also improved. Furthermore, the device with HfAlO x layer exhibits long retention time (>104 s at 85 °C), high on/off ratio and more than 103 cycles of endurance at atmospheric environment. Those substantial improvements in IGZO memory device are attributed to the interface effects with a HfAlO x insertion layer. With such layer, the formation and rupture locations of Ag conductive filaments are better regulated and confined, thus an improved performance stability. [ABSTRACT FROM AUTHOR]

Over the last few decades, despite significant advancements in oxide-based ReRAM (resistive random-access memory) devices, science and technology have faced many obstacles, notably, those relating to data, conducting filament rupture and device uniformity issues. The density functional theory technique based on the first-principles calculations is used to calculate structural, electronic and magnetic properties of pure CeO2, CeO2 + VO, Ce1-xTmxO2 + VO (Tm = Co, Ni). The effect of oxygen vacancy and transition metal doping on the electronic structures is investigated using generalized gradient approximation developed by Perdew, Burke and Ernzerhof. The role of oxygen vacancies has been evaluated in this study as they play an important role in the development as well as rapturing of conducting filaments. Pristine ceria (CeO2) has more structural stability compared to compounds with oxygen vacancies and transition metal doping. It is evident from energy band structures that additional states developed in CeO2 + VO and Ce1-xTmxO2 + VO (Tm = Co, Ni) compared to CeO2. These additional states result in enhanced conductivity of these compounds. From magnetic properties, we can explain that Ce1-xCoxO2 + VO have the highest magnetic moments compared to other compounds. CeO2 can be used effectively in various technological applications like catalysts, medicine, solar reactors, cosmetics, data storage, optics and energy storage applications, but here we are only interested in data storage (memory) applications. [ABSTRACT FROM AUTHOR]

Lateral electrochemical metallization (ECM) cells are fabricated with a combined spacer/damascene process. The process allows the realization of nanoscale geometrical distances between the two electrodes independent of lithography. Such lateral ECM cells are an essential part in a reconfigurable interconnect system that may yield a strongly increased connectivity in artificial neural networks. The lateral cells show memristive properties comparable to vertical cells with switching voltages in the range of −1.5V to 2.5V. The influence of electrode line edge roughness on SET kinetics of such lateral cells is investigated via kinetic Monte Carlo simulations, finding a minor influence on SET time variability.

Memristive devices are promising candidates for analog computing applications such as neuromorphic computation. Larger dynamic ranges and more sufficient multilevel states can enable the significant development of memristor‐based utilizations. Herein, a method to improve the analog switching performance of memristors through a hybrid tuning (coarse and fine tuning) of two sub‐filaments is demonstrated. The creation of sub‐filaments inside the dielectric switching layer is realized by deploying Pt metal islands in the switching layer. Given the different material stack configurations of the two sub‐filaments, they exhibit different switching properties to play the roles of coarse and fine tuning respectively in the memristor. Based on the above mechanism, a Pt/Ta/Al2O3/Pt island/Al2O3‐x/TiOy/Al2O3‐x/Pt memristor is proposed and fabricated. Through the hybrid tuning of two sub‐filaments, a combined dynamic range of 600 Ω to 50 kΩ is achieved. Compared to the reference Pt/Ta/Al2O3/Pt memristors (dynamic range: 600 Ω to 8 kΩ), both dynamic range and multilevel resistance states are increased significantly. Meanwhile, the energy efficiency is improved because the resistance of tunable states can be set to larger values. Furthermore, this mechanism can be incorporated into various existing memristors to improve their dynamic range and multilevel states, which extensively enriches the applications of memristors. [ABSTRACT FROM AUTHOR]

Abstract Dielectric breakdown (BD) is known to cause component failure in electronic devices and high‐voltage power lines over many decades. In recent years, this failure mechanism has been exploited to intentionally form nanoscale filaments in resistive random‐access‐memory (ReRAM) devices for artificial intelligence (AI). The statistical nature of this failure mechanism, known as the inverse size scaling law based on the weakest‐link theory, dictates the ever‐higher forming voltages for ReRAM devices, in turn, requiring additional peripheral transistors. This law also causes diminishing lifetimes of electronic components for future generations of very‐large‐integrated circuits (VLSI) technology. Currently, the semiconductor industry faces these scaling barriers limiting the miniaturization of both VLSI and AI hardware technology. Here, experimental evidence of a reverse area dependence is presented by introducing an innovative fabrication process with a hydrogen‐plasma‐treated layer in a bilayer HfO2 structure. Using joint order statistics rather than traditional extreme‐value statistics, a physics‐based statistical model is developed in agreement with the experimental data, thus demonstrating that there is no fundamental reason preventing this law from being reversed or altered. These findings will have a significant impact on both technology scaling and fabrication innovation for electronic and/or bioinspired nanomaterials; moreover, stimulate much research in physics, statistics, and reliability.

We present a resistance switching device that exhibits analogue potentiation and depression of conductance under the same voltage polarity. This contrasts with previously studied devices that potentiate and depress under opposite polarities. We refer to this mode of operation as the subthreshold regime due to it occurring at voltage or current biases that are insufficient to produce discrete or non-volatile switching. This behaviour has the potential to reduce the complexity of neuronal and synaptic circuitry in neuromorphic computing by removing the need for voltage pulses of both positive and negative polarities. The characteristically long timescales may also help replicate bio-realistic timings. In this article, we detail how to induce this unique behaviour, how to tune its properties to a desired response, and finally, we demonstrate one potential application. [ABSTRACT FROM AUTHOR]

With the development of artificial intelligence and the importance of big data processing, research is actively underway to break away from data bottlenecks and modern Von Neumann architecture computing structures that consume considerable energy. Among these, hardware technology for neuromorphic computing is in the spotlight as a next-generation intelligent hardware system because it can efficiently process large amounts of data with low power consumption by simulating the brain's calculation algorithm. In addition to memory devices with existing commercial structures, various next-generation memory devices, including memristors, have been studied to implement neuromorphic computing. In this study, we evaluated the synaptic characteristics of a resistive random access memory (ReRAM) with a Ru/HfOx/TiN structure. Under a series of presynaptic spikes, the device successfully exhibited remarkable long-term plasticity and excellent nonlinearity properties. This synaptic device has a high operating speed (20 ns, 50 ns), long data retention time (> 2 h @85 ℃) and high recognition rate (94.7%). Therefore, we propose that memory and learning capabilities can be used as promising HfOx-based memristors in next-generation artificial neuromorphic computing systems. [ABSTRACT FROM AUTHOR]

Memristive devices are the subject of extensive studies nowadays. While the Dynamic Route Map is a powerful tool for analyzing the response of first-order memristors under DC stimuli, the development of an equivalent tool for investigating the response of these devices to AC stimuli is still an open question. Recently, Pershin and Slipko introduced a graphic method, which we name Time Average State Dynamic Route (TA-SDR), applicable to study first-order memristors subject to periodic rectangular pulse train-based stimuli. In this paper we introduce an alternative investigation tool, referred to as State Change Per Cycle Map (SCPCM), which is applicable in these very same scenarios. The novel analysis technique, inspired by the work of the French mathematician Henri Poincaré, reduces the investigation of a first-order non-autonomous continuous-time system to a simpler study of a first-order discrete-time map. A State Change Per Cycle Map defines precisely how the stimulus modulates each of the admissible device memory states over one input cycle. It is derivable either by means of numerical simulations, where a model for the ReRAM cell is available, or experimentally, in the case where the device memory state is accessible. While the predictive capability of a TA-SDR is limited to those case studies, where the AC periodic voltage signal applied across the device induces negligible changes in the respective memory state over each cycle, the conclusions drawn by analyzing a SCPCM have general validity, irrespective of the properties of the stimulus. The advantages of the novel analysis method for periodically driven ReRAM cells over the classical TA-SDR tool are highlighted through a number of case studies, some of which reveal the interesting capability of the ReRAM cell to display multiple oscillatory operating modes upon periodic stimulation via trains with a suitable number of SET and RESET pulses per period.

Resistive random access memories (ReRAM) have drawn attention of researchers due to their unique properties with applications in in-memory computing, which allows storage and computation in the same unit. This mitigates one of the major limitations in current computing architectures, where for each computation we require to move data from memory to processor or vice versa, which incurs immense amount of energy overheads. Among the various technologies for implementing ReRAM, memristor is considered to be one of the most desirable candidates due to its small size, low power consumption, and high data retention. Such ReRAM systems are often fabricated in the form of crossbar for compact layout. However, they suffer from various challenges, one of the major ones being the sneak-path problem during reading of cell values. The read operation is mostly disturbed by sneak-path currents that can result in incorrect reading of the cell. This paper presents a new approach for reading the cell values in memristive crossbars, which is capable of avoiding erroneous read operations caused by sneak-paths. It also supports parallel operations whereby multiple memristor states can be read in a single cycle. A straightforward approach for reading all the cells in an n×ncrossbar, where the read operation is performed sequentially, requires O(n2)cycles, whereas the proposed approach requires O(n)cycles.

Resistive memory (ReRAM) or memristor devices offer the prospect of more efficient computing. While memristors have been used for a variety of computing systems, their usage has gained significant popularity in the domain of deep learning. Weight matrices in deep neural networks can be mapped to crossbar architectures with memristive junctions, generally resulting in superior performance and energy efficiency. However, the nascent nature of ReRAM technology is directly associated with the presence of inherent non-idealities in the ReRAM devices currently available. Deep neural networks have already been shown to be susceptible to adversarial attacks, often by targeting vulnerabilities in the networks’ internal representation of input data. In this paper, we explore the causal relationship between device-level non-idealities in ReRAM devices and the classification performance of memristor-based neural network accelerators. Specifically, our aim is to generate images which bypass adversarial defense mechanisms in software neural networks but trigger non-trivial performance discrepancies in ReRAM-based neural networks. To this end, we have proposed a framework to generate adversarial images in the hypervolume between the two decision boundaries, thereby leveraging non-ideal device behavior for performance detriment. We employ state-of-the-art tools in explainable artificial intelligence to characterize our adversarial image samples, and derive a new metric to quantify susceptibility to adversarial attacks at the pixel and device-levels.

Through Random Telegraph Noise (RTN) analysis, valuable information can be provided about the role of defect traps in fine tuning and reading of the state of a nanoelectronic device. However, time domain analysis techniques exhibit their limitations in case where unstable RTN signals occur. These instabilities are a common issue in Multi-Level Cells (MLC) of resistive memories (ReRAM), when the tunning protocol fails to find a perfectly stable resistance state, which in turn brings fluctuations to the RTN signal especially in long time measurements and cause severe errors in the estimation of the distribution of time constants of the observed telegraphic events, i.e., capture/emission of carriers from traps. In this work, we analyze the case of the unstable filaments in silicon nitride-based ReRAM devices and propose an adaptive filter implementing a moving-average detrending method in order to flatten unstable RTN signals and increase sufficiently the accuracy of the conducted measurements. The τe and τc emission/capture time constants of the traps, respectively, are then calculated and a cross-validation through frequency domain analysis (Lorentzian fitting) was performed proving that the proposed method is accurate.

This paper proposes two different approaches to studying resistive switching of oxide thin films using scratching probe nanolithography of atomic force microscopy (AFM). These approaches allow us to assess the effects of memristor size and top-contact thickness on resistive switching. For that purpose, we investigated scratching probe nanolithography regimes using the Taguchi method, which is known as a reliable method for improving the reliability of the result. The AFM parameters, including normal load, scratch distance, probe speed, and probe direction, are optimized on the photoresist thin film by the Taguchi method. As a result, the pinholes with diameter ranged from 25.4 ± 2.2 nm to 85.1 ± 6.3 nm, and the groove array with a depth of 40.5 ± 3.7 nm and a roughness at the bottom of less than a few nanometers was formed. Then, based on the Si/TiN/ZnO/photoresist structures, we fabricated and investigated memristors with different spot sizes and TiN top contact thickness. As a result, the HRS/LRS ratio, USET, and ILRS are well controlled for a memristor size from 27 nm to 83 nm and ranged from ~8 to ~128, from 1.4 ± 0.1 V to 1.8 ± 0.2 V, and from (1.7 ± 0.2) × 10−10 A to (4.2 ± 0.6) × 10−9 A, respectively. Furthermore, the HRS/LRS ratio and USET are well controlled at a TiN top contact thickness from 8.3 ± 1.1 nm to 32.4 ± 4.2 nm and ranged from ~22 to ~188 and from 1.15 ± 0.05 V to 1.62 ± 0.06 V, respectively. The results can be used in the engineering and manufacturing of memristive structures for neuromorphic applications of brain-inspired artificial intelligence systems. [ABSTRACT FROM AUTHOR]

With decreasing die size and the ability to store multiple bits in a single cell, resistive random access memory (ReRAM) can be used to increase storage density, making it a promising technology for the next generation of memory. However, multi-level write operations suffer from impairments such as large latency, high energy consumption, and reliability issues. In this paper, we study different mechanisms affecting the "multi-level incremental step pulse with verify algorithm" (M-ISPVA) on a 1-transistor-1-resistor (1T1R) model in transient simulation at the component and the circuit level with focus on resistance control and energy consumption during the entire process of state transitions. By dividing the M-ISPVA into a triggering and a controlling period, we discovered the transistor to operate in the ohmic region during the triggering period as a voltage-controlled resistance and in the saturation region during the controlling period as a voltage-controlled current limiter. Controlling the gate voltage in the triggering period can move the triggering point to a desired write voltage and in the controlling period can increase or decrease resistance steps per pulse to attain a desired speed of resistance change. In addition, the major energy portion is consumed for reset operation during triggering and for set operation during the controlling period. To optimize write performance, extra precaution must be taken when defining resistance states with target read-out current and gate voltage with the focus on evenly balanced latencies between all transitions. A direct multi-level write operation shows 67.5 % latency and 62.5 % energy saving compared to indirect ones, but suffers from only unidirectional control, making it non-feasible. In case of a 4 k bit memory, the more reliable M-ISPVA faces almost 37 % higher latency and energy compared to the basic ISPVA. [ABSTRACT FROM AUTHOR]

This review focuses on oxide memristors for resistive random access memory (ReRAM). Possible practical implementations of ReRAM and the problem of leakage through neighboring elements in ReRAM are considered. The main types of resistive switching in memristors are briefly described and the main mechanisms of resistive switching are analyzed. The main characteristics of memristors required for ReRAM are also described. Some memristor structures based on oxides of titanium, silicon, tantalum, and hafnium, as well as multilayer oxide structures are analyzed. The current problems in the creation of ReRAM are highlighted. [ABSTRACT FROM AUTHOR]

In the context of computing in resistive memories (ReRAM), the implementation of threshold logic gates (TLGs) with memristors has been especially investigated for programable in-memory logic implementations. In this work we focus on two circuit design concepts for threshold logic with memristors: the voltage divider and the voltage adder. We provide an analytical exploration of the impact of the HRS-to-LRS ratio of memristors on the performance of every circuit and highlight the advantages of the voltage adder approach. Through experimental results from a proof-of-concept circuit, implemented using self-directed channel (SDC) memristors by Knowm Inc., we validated the conclusions derived from the theoretical analysis for computational memory structures supporting threshold logic gates. Moreover, we present the design and simulation of a bitline driver and sensing circuitry for a 1T1R array, where the proposed threshold logic scheme can seamlessly fit, thus providing solutions towards the development of robust and reliable computational ReRAM modules. [ABSTRACT FROM AUTHOR]

A new architecture has become necessary owing to the power consumption and latency problems of the von Neumann architecture. A neuromorphic memory system is a promising candidate for the new system as it has the potential to process large amounts of digital information. A crossbar array (CA), which consists of a selector and a resistor, is the basic building block for the new system. Despite the excellent prospects of crossbar arrays, the biggest obstacle for them is sneak current, which can cause a misreading between the adjacent memory cells, thus resulting in a misoperation in the arrays. The chalcogenide-based ovonic threshold switch (OTS) is a powerful selector with highly nonlinear I–V characteristics that can be used to address the sneak current problem. In this study, we evaluated the electrical characteristics of an OTS with a TiN/GeTe/TiN structure. This device shows nonlinear DC I–V characteristics, an excellent endurance of up to 109 in the burst read measurement, and a stable threshold voltage below 15 mV/dec. In addition, at temperatures below 300 °C, the device exhibits good thermal stability and retains an amorphous structure, which is a strong indication of the aforementioned electrical characteristics. [ABSTRACT FROM AUTHOR]

Resistive Random Access Memory (ReRAM) is a novel non-volatile memory technology, with potential applications spanning high-density memory and embedded memory in various non-von Neumann computing architectures. This study investigated the dependency of ReRAM switching parameters on the stoichiometry of the tantalum oxide switching layer. Devices were fabricated using reactive sputtering where oxygen partial pressure was varied during deposition of the switching layer. X-ray photoelectron spectroscopy was employed to evaluate the resulting tantalum oxide film composition, showing distinct Ta sub-oxides for each oxygen partial pressure implemented during reactive sputtering. Electrical characterization revealed optimal device performance, with sub-3 V forming voltage and memory window >10 for ReRAM devices deposited with 0.14 mTorr pO 2. Devices fabricated at lower pO 2 and excessively high pO 2 failed to exhibit resistive switching behavior. [ABSTRACT FROM AUTHOR]

• The role of a 3 nm Al 2 O 3 on top of stoichiometric LPCVD SiN x MIS RRAM cells is investigated. • The devices can be SET at different resistance levels by varying the I CC. • SET/RESET voltages are higher compared to the reference sample, corresponding to the voltage drop on the Al 2 O 3. • A compact model can be successfully used to simulate the I-V curves of our devices in circuit level designs. • Impedance spectroscopy measurements revealed that the conduction in SiN x is mostly governed by trap-to-trap tunneling mechanisms. The role of a 3 nm Al 2 O 3 layer on top of stoichiometric LPCVD SiN x MIS RRAM cells is investigated by using various electrical characterization techniques. The conductive filament formation is explained, and a compact model is used to fit the current–voltage curves and find its evolution during each operation cycle. The conduction in SiN x is also studied. [ABSTRACT FROM AUTHOR]

The demand for computation driven by machine learning and deep learning applications has experienced exponential growth over the past five years (Sevilla et al 2022 2022 International Joint Conference on Neural Networks (IJCNN) (IEEE) pp 1-8), leading to a significant surge in computing hardware products. Meanwhile, this rapid increase has exacerbated the memory wall bottleneck within mainstream Von Neumann architectures (Hennessy and Patterson et al 2011 Computer architecture: a quantitative approach (Elsevier)). For instance, NVIDIA graphical processing units (GPUs) have gained nearly a 200x increase in fp32 computing power, transitioning from P100 to H100 in the last five years (NVIDIA Tesla P100 2023 ( https://www.nvidia.com/en-us/data-center/tesla-p100/ ); NVIDIA H100 Tensor Core GPU 2023 ( https://www.nvidia.com/en-us/data-center/h100/ )), accompanied by a mere 8x scaling in memory bandwidth. Addressing the need to mitigate data movement challenges, process-in-memory designs, especially resistive random-access memory (ReRAM)-based solutions, have emerged as compelling candidates (Verma et al 2019 IEEE Solid-State Circuits Mag. 11 43–55; Sze et al 2017 Proc. IEEE 105 2295–329). However, this shift in hardware design poses distinct challenges at the design phase, given the limitations of existing hardware design tools. Popular design tools today can be used to characterize analog behavior via SPICE tools (PrimeSim HSPICE 2023 ( https://www.synopsys.com/implementation-and-signoff/ams-simulation/primesim-hspice.html )), system and logical behavior using Verilog tools (VCS 2023 ( https://www.synopsys.com/verification/simulation/vcs.html )), and mixed signal behavior through toolbox like CPPSIM (Meninger 2023 ( https://www.cppsim.org/Tutorials/wideband_fracn_tutorial.pdf )). Nonetheless, the design of in-memory computing systems, especially those involving non-CMOS devices, presents a unique need for characterizing mixed-signal computing behavior across a large number of cells within a memory bank. This requirement falls beyond the scope of conventional design tools. In this paper, we bridge this gap by introducing the ReARTSim framework—a GPU-accelerated mixed-signal transient simulator for analyzing ReRAM crossbar array. This tool facilitates the characterization of analog circuit and device behavior on a large scale, while also providing enhanced simulation performance for complex algorithm analysis, sign-off, and verification.

Resistively switching electrochemical metallization memory cells are gaining huge interest since they are seen as promising candidates and basic building blocks for future computation-in-memory applications. However, especially filamentary-based memristive devices suffer from inherent variability, originating from their stochastic switching behavior. A variability-aware compact model of electrochemical metallization memory cells is presented in this study and verified by showing a fit to experimental data. It is an extension of the deterministic model. Since this extension consists of several different features allowing for a realistic variability-aware fit, it depicts a unique model comprising physics-based, stochastically and experimentally originating variabilities and reproduces them well. In addition, a physics-based model parameter study is executed, which enables a comprehensive view into the device physics and presents guidelines for the compact model fitting procedure.