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Virtualization plays a crucial role in successfully integrating multiple real-time applications on a single platform. Through virtualization, different applications can run in independent virtual machines, isolated from each other to prevent mutual interference. This paper considers partitioned fixed priority (P-FP) scheduling for tasks and servers on the multi-core virtualization platform with non-preemptive resource sharing. The solution for P-FP scheduling on multi-core virtualization environments typically uses vMPCP, an extension protocol of the well-known Multiprocessor Priority Ceiling Protocol (MPCP), to address the problem of resource sharing among real-time application tasks. However, the existing analysis of Worst-Case Blocking Time (WCBT) for the P-FP+vMPCP scheduling tends to be overly conservative, resulting in many schedulable task sets being incorrectly classified as unschedulable. Consequently, it leads to wasted system resources and degraded performance. To mitigate this issue and reduce the pessimism of existing analysis, we propose an improved WCBT analysis. This analysis bounds the maximum blocking time that tasks experience when each job from the same task requires to access the same type of non-preemptive global resource multiple times. As a result, it enhances the accuracy over prior work and obtains more precise Worst-Case Response Time (WCRT) for tasks. In our experiments, the WCRT-based schedulability test is adopted to evaluate the schedulability of tasks. Additionally, we do not consider additional scheduling costs, as no online decisions are required. Experimental results demonstrate that our proposed method outperforms the latest advanced methods in terms of the schedulability rate of tasks. Specifically, the schedulable task sets are increased by approximately 47.7% on average.

The heterogeneity of the multiple processing elements (PEs) is a feature of real-time embedded systems. General-purpose processors and several embedded processors, as well as dedicated high-speed interfaces, are among these elements. Communication between the processors is among the most significant characteristics of developing such complex systems. Furthermore, synchronization is a common issue during interprocessor communication in embedded systems. Debugging and testing such systems is time-consuming, difficult, and laborious, with the majority of the complexities centered on debugging real-time interprocessor communication, such as synchronization in terms of timing and accuracy. While the hardware design features of heterogeneous multiprocessor real-time embedded systems have received a lot of attention, the design and development of software-based solutions still have the potential to be addressed. In particular, software-based testing becomes challenging due to interprocessor communication and the synchronization of real-time applications. A knowledge-based technique that aids in testing high-speed serial interfaces in multiprocessor-based real-time embedded systems is proposed that needs debugging in real time while an application is running. It is becoming much more important to test and validate these interfaces in real time as the demand for high data transmission rates increases. The presented work uses a technique to simulate, create and enhance the knowledge base used as correlation-based error detection that reduces the development time. The proposed technique helps in detecting synchronization-related errors that occur during communication among multiple high-speed serial interfaces. The presented work also lists a series of experiments to validate the effectiveness of the proposed technique. The results show that the presented techniques are effective for error identification in real-time embedded systems. [ABSTRACT FROM AUTHOR]

Mechatronic systems, like mobile robots, are fairly complex. They are composed of electromechanical actuation components and sensing elements supervised by microcontrollers running complex embedded software. This paper proposes a novel approach to aid mobile robotics developers in adopting a rigorous development process to design and verify the robot's detection and mitigation capabilities against random hardware failures affecting its sensors or actuators. Unfortunately, assessing the interactions between the various safety/mission-critical subsystem is quite complex. The failure mode effect analysis (FMEA) alongside an analysis of the failure detection capabilities (FMEDA) are the state-of-the-art methodologies for performing such an analysis. Various guidelines are available, and the authors decided to follow the one released by AIAG&VDA in June 2019. Since the robot's behavior is based on embedded software, the FMEA has been integrated with the hardware/software interaction analysis described in the ECSS-Q-ST-30-02C manual. The core of this proposal is to show how a simulation-based approach, where the mechanical and electrical/electronic components are simulated alongside the embedded software, can effectively support FMEA. As a benchmark application, we considered the mobility system of a proof-of-concept assistance rover for Mars exploration designed by the D.I.A.N.A. student team at Politecnico di Torino. Thanks to the adopted approach, we described how to develop the detection and mitigation strategies and how to determine their effectiveness, with a particular focus on those affecting the sensors. [ABSTRACT FROM AUTHOR]

Real-time inference of deep learning models on embedded and energy-efficient devices becomes increasingly desirable with the rapid growth of artificial intelligence on edge. Specifically, to achieve superb energy-efficiency and scalability, efficient parallelization of single-pass deep neural network (DNN) inference on chip multiprocessor (CMP) architectures is urgently required by many time-sensitive applications. However, as the number of processing cores scales up and the performance of cores has grown much fast, the on-chip inter-core data movement is prone to be a performance bottleneck for computation. To remedy this problem and further improve the performance of network inference, in this work, we introduce a communication-aware DNN parallelization technique called CAP, by exploiting the elasticity and noise-tolerance of deep learning algorithms on CMP. Moreover, in the hope that the conducted studies can provide new design values for real-time neural network inference on embedded chips, we also have evaluated the proposed approach on both multi-core Neural Network Accelerators (NNA) chips and general-purpose chip-multiprocessors. Our experimental results show that the proposed CAP can achieve 1.12×-1.65× system speedups and 1.14×-2.70× energy efficiency for different neural networks while maintaining the inference accuracy, compared to baseline approaches. [ABSTRACT FROM AUTHOR]

To build a smart home that assists people with disabilities, we urgently need a non-invasive user identification system capable of recognizing family members in real-time and being easy to use. Existing systems face issues such as privacy concerns from cameras, inconvenience from needing physical contact with sensors, and the requirement to always carry a specific device. Additionally, these systems typically depend on edge nodes to collect data and then transfer it to cloud servers for high-performance inference. This dependency leads to network delays, hindering real-time service, and introducing security issues. To address these requirements, this paper presents a real-time non-invasive user identification system that recognizes users as they step on a foot pad. This study introduces an edge node designed to measure real-time foot pressure distribution data, along with a preprocessing system for data generalization. Additionally, we propose a system that performs real-time user inference using only resource-constrained edge nodes to overcome the challenges of cloud-based systems, including addressing security issues without specific protocols. To achieve this, we optimized various deep learning-based user identification models to be executable on edge nodes and then compared their performance. As a result, using a ResNet18 model through pruning and post quantization training with integer, we achieved inference within 1.5 s with 85% accuracy. Compared to the worst-performing AlexNet, the ResNet18 model shows a substantial reduction in model size by approximately 33%, a decrease in memory usage by about 80%, and a significant increase in inference speed by over tenfold. • It uses foot pressure for user recognition, overcoming biometric impracticalities. • Conducting all tasks at edge node, we resolved issues of security and predictability. • Data preprocessing overcame limits, enabling effective learning with minimal data. • To select the optimal model effectively, we evaluated the AI models comprehensively. • A user-friendly real-time recognition system expandable to smart homes for patients. [ABSTRACT FROM AUTHOR]

Emerging safety-critical systems require high-performance data-parallel architectures and, problematically, ones that can guarantee tight and safe worst-case execution times. Given the complexity of existing architectures like GPUs, it is unlikely that sufficiently accurate models and algorithms for timing analysis will emerge in the foreseeable future. This motivates our work on Sim-D, a clean-slate approach to designing a real-time data-parallel architecture. Sim-D enforces a predictable execution model by isolating compute- and access resources in hardware. The DRAM controller uninterruptedly transfers tiles of data, requested by entire work-groups. This permits work-groups to be executed as a sequence of deterministic access- and compute phases, scheduling phases from up to two work-groups in parallel. Evaluation using a cycle-accurate timing model shows that Sim-D can achieve performance on par with an embedded-grade NVIDIA TK1 GPU under two conditions: applications refrain from using indirect DRAM transfers into large buffers, and Sim-D's scratchpads provide sufficient bandwidth. Sim-D's design facilitates derivation of safe WCET bounds that are tight within 12.7 percent on average, at an additional average performance penalty of $\sim$ ∼ 9.2 percent caused by scheduling restrictions on phases. [ABSTRACT FROM AUTHOR]

In this article, we present an Online Learning Artificial Neural Network (ANN) model that is able to predict the performance of tasks in lower frequency levels and safely optimize real-time embedded systems’ power saving operations. The proposed ANN model is supported by feature selection, which provides the most relevant variables to describe shared resource contention in the selected multicore architecture. The variables are used at runtime to produce a performance trace that encompasses sufficient information for the ANN model to predict the impact of a frequency change on the performance of tasks. A migration heuristic encompassing a weighted activity vector is combined with the ANN model to dynamically adjust frequencies and also to trigger task migrations among cores, enabling further optimization by solving resource contentions and balancing the load among cores. The proposed solution achieved energy-savings of 24.97 percent on average when compared to the run-to-end approach, and it did it without compromising the criticality of any single task. The overhead incurred in terms of execution time was 0.1791 percent on average. Each prediction added 15.3585 $\mu s$ μ s on average and each retraining cycle triggered at frequency adjustments was never larger than 100 $\mu s$ μ s . [ABSTRACT FROM AUTHOR]

The exact response time analysis for fixed priority scheduling (FPS) in the lowest priority first-based feasibility tests is commonly required as a part of system design tools. This letter proposes an efficient method for this, which we named incremental lower bound (ILB) calculation method. Compared to the best algorithm that has been known so far, which is the incremental calculation method, ILB reduces the feasibility test iterations/run times by more than 38% and 20% regardless of varying utilization and the number of tasks in task sets. [ABSTRACT FROM AUTHOR]

Mechatronic systems, like mobile robots, are fairly complex. They are composed of electromechanical actuation components and sensing elements supervised by microcontrollers running complex embedded software. This paper proposes a novel approach to aid mobile robotics developers in adopting a rigorous development process to design and verify the robot’s detection and mitigation capabilities against random hardware failures affecting its sensors or actuators. Unfortunately, assessing the interactions between the various safety/mission-critical subsystem is quite complex. The failure mode effect analysis (FMEA) alongside an analysis of the failure detection capabilities (FMEDA) are the state-of-the-art methodologies for performing such an analysis. Various guidelines are available, and the authors decided to follow the one released by AIAG&VDA in June 2019. Since the robot’s behavior is based on embedded software, the FMEA has been integrated with the hardware/software interaction analysis described in the ECSS-Q-ST-30-02C manual. The core of this proposal is to show how a simulation-based approach, where the mechanical and electrical/electronic components are simulated alongside the embedded software, can effectively support FMEA. As a benchmark application, we considered the mobility system of a proof-of-concept assistance rover for Mars exploration designed by the D.I.A.N.A. student team at Politecnico di Torino. Thanks to the adopted approach, we described how to develop the detection and mitigation strategies and how to determine their effectiveness, with a particular focus on those affecting the sensors.

Real-time and embedded systems are required to adapt their behavior and structure to runtime unpredicted changes in order to maintain their feasibility and usefulness. These systems are generally more difficult to specify and verify owning to their execution complexity. Hence, ensuring the high-level design and the early verification of system adaptation at runtime is very crucial. However, existing runtime model-based approaches for adaptive real-time and embedded systems suffer from shortcoming linked to efficiently and correctly managing the adaptive system behavior, especially that a formal verification is not allowed by modeling languages such as UML and MARTE profile. Moreover, reasoning about the correctness and the precision of high-level models is a complex task without the appropriate tool support. In this work, we propose an MDE-based framework for the specification and the verification of runtime adaptive real-time and embedded systems. Our approach stands for Event-B method to formally verify resources behavior and real-time constraints. In fact, thanks to MDE M2T transformations, our proposal translates runtime models into Event-B specifications to ensure the correctness of runtime adaptive system properties, temporal constrains and nonfunctional properties using Rodin platform. A flood prediction system case study is adopted for the validation of our proposal. [ABSTRACT FROM AUTHOR]

The ever-increasing need for computational power in embedded devices has led to the adoption heterogeneous SoCs combining a general purpose CPU with a data parallel accelerator. These systems rely on a shared main memory (DRAM), which makes them highly susceptible to memory interference. A promising software technique to counter such effects is the Predictable Execution Model (PREM). PREM ensures robustness to interference by separating programs into a sequence of memory and compute phases, and by enforcing a platform-level schedule where only a single processing subsystem is permitted to execute a memory phase at a time. This article demonstrates for the first time how PREM can be applied to heterogeneous SoCs, based on a synchronization technique for memory isolation between CPU and GPU plus a compiler to transform GPU kernels into PREM-compliant codes. For compute bound GPU workloads sharing the DRAM bandwidth 50/50 with the CPU we guarantee near-zero timing varibility at a performance loss of just 59 percent, which is one to two orders of magnitude smaller than the worst case we see for unmodified programs under memory interference. [ABSTRACT FROM AUTHOR]

Cache sharing technique is critical in multi-core and multi-threading systems. It potentially delays the execution of real-time applications and makes the prediction of the worst-case execution time (WCET) of real-time applications more challenging. Prioritized cache has been demonstrated as a promising approach to address this challenge. Instead of the conventional prioritized cache schemes realized at the architecture level by using cache controllers, this work presents two prioritized least recently used (LRU) cache replacement circuits that directly accomplish the prioritization inside the cache circuits, hence significantly reduces the cache access latency. The performance, hardware and power overheads due to the proposed prioritized LRU circuits are investigated based on a 65 nm CMOS technology. It shows that the proposed circuits have very low overhead compared to conventional cache circuits. The presented techniques will lead to more effective prioritized shared cache implementations and benefit the development of high-performance real-time systems. [ABSTRACT FROM AUTHOR]

Embedded systems consist of one or more processing units which are completely encapsulated by the devices under their control, and they often have stringent timing constraints associated with their functional specification. Previous research has considered the performance of different types of task scheduling algorithm and developed associated timing analysis techniques for such systems. Although preemptive scheduling techniques have traditionally been favored, rapid increases in processor speeds combined with improved insights into the behavior of non-preemptive scheduling techniques have seen an increased interest in their use for real-time applications such as multimedia, automation and control. However when non-preemptive scheduling techniques are employed there is a potential lack of error confinement should any timing errors occur in individual software tasks. In this paper, the focus is upon adding fault tolerance in systems using non-preemptive deadline-driven scheduling. Schedulability conditions are derived for fault-tolerant periodic and sporadic task sets experiencing bounded error arrivals under non-preemptive deadline scheduling. A timing analysis algorithm is presented based upon these conditions and its run-time properties are studied. Computational experiments show it to be highly efficient in terms of run-time complexity and competitive ratio when compared to previous approaches.

The importance of physically contiguous memory has increased in modern computing environments, including both low- and high-end systems. Existing physically contiguous memory allocators generally have critical limitations. For example, the most commonly adopted solution, the memory reservation technique, wastes a significant amount of memory space. Scatter/Gather direct memory access (DMA) and input-output memory management units (IOMMUs) avoid this problem by utilizing additional hardware for address space virtualization. However, additional hardware means an increase in costs and power consumption, which is especially disadvantageous for small systems and they do not provide real contiguous memory. Linux Contiguous Memory Allocator (CMA) aims to provide both contiguous memory allocation and to maximize memory utilization based on page migration, but they suffer from unpredictably long latency and a high probability of allocation failure. Therefore, we introduce a new solution to this problem, the guaranteed contiguous memory allocator (GCMA). This guarantees efficient memory space utilization, short latency, and successful allocation. The GCMA uses a reservation scheme and increases memory utilization by sharing the memory with immediately discardable data. Our evaluation of a GCMA on a Raspberry Pi 2 finds a latency that is 15-130 times lower compared to a CMA, and a latency that is up to 10 times lower when taking a photo. Using a large working set in a memory-fragmented high-end system, the GCMA is able to produce a 2.27x speedup. [ABSTRACT FROM AUTHOR]

This paper introduces a new technique that perturbs split-gate NOR Flash memory cells and extracts randomness of read noise to generate true random numbers. Flash memory cells exhibit threshold voltage fluctuations during read operations caused by thermal noise and random telegraph noise effects. Recent proposals demonstrate how these inherent properties of Flash memory cells can be used to create true random numbers in modern NAND Flash memories. However, they cannot be directly applied to NOR Flash memories in microcontrollers that have different architecture, improved data retention, high endurance, and are not as susceptible to noise as high-density NAND Flash memories. The proposed technique is experimentally demonstrated and evaluated using a family of commercial microcontrollers. The evaluation shows that it enables extraction of high-throughput random sequences that pass the NIST statistical tests. Advantages of the proposed technique are as follows: (a) it does not require any special hardware and/or interface modifications, (b) it is robust, cost-effective, and high-throughput, (c) it is entirely implemented in software, and (d) it is flexible and can be tailored to work in low-end microcontrollers that are often resource- or cost-constrained. [ABSTRACT FROM AUTHOR]

Support Vector Machines (SVMs) are considered as a state-of-the-art classification algorithm capable of high accuracy rates for a different range of applications. When arranged in a cascade structure, SVMs can efficiently handle problems where the majority of data belongs to one of the two classes, such as image object classification, and hence can provide speedups over monolithic (single) SVM classifiers. However, the SVM classification process is still computationally demanding due to the number of support vectors. Consequently, in this paper we propose a hardware architecture optimized for cascaded SVM processing to boost performance and hardware efficiency, along with a hardware reduction method in order to reduce the overheads from the implementation of additional stages in the cascade, leading to significant resource and power savings. The architecture was evaluated for the application of object detection on 800×600 resolution images on a Spartan 6 Industrial Video Processing FPGA platform achieving over 30 frames-per-second. Moreover, by utilizing the proposed hardware reduction method we were able to reduce the utilization of FPGA custom-logic resources by ∼30%, and simultaneously observed ∼20% peak power reduction compared to a baseline implementation. [ABSTRACT FROM AUTHOR]

Many high-level vision applications apply image segmentation during preprocessing to improve their overall execution efficiency. The applied segmentation technique must, therefore, be highly efficient, or otherwise would counteract any system performance improvement. Existing segmentation approaches often fail to meet real-time processing standards and exhibit extremely slow frame rates when applied to high-resolution images. This paper presents a highly optimized serial implementation of a novel image segmentation approach known as leap segmentation, which achieves frame rates exceeding that of the state-of-the art: it segments more than 80 fps on 640 × 360 images and more than 20 fps on high-resolution (1,280 × 720) images. (All images used for evaluation in this paper use a 24-bit red-green-blue color representation with 8 bits per color). We analyze leap segmentation further for areas of possible parallelization and restructure it for use on a parallel processing system to achieve additional speed-up. On a multi-core, mobile processing system with four threads, our multi-core leap segmentation implementation achieves frame rates of over 114 fps on 640 × 360 images and more than 31 fps on 1,280 × 720 images, thus easily exceeding real-time processing standards. [ABSTRACT FROM AUTHOR]

Synchronous dynamic random access memories (SDRAMs) are widely employed in multi- and many-core platforms due to their high-density and low-cost. Nevertheless, their benefits come at the price of a complex two-stage access protocol, which reflects their bank-based structure and an internal level of explicitly managed caching. In scenarios in which requestors demand real-time guarantees, these features pose a predictability challenge and, in order to tackle it, several SDRAM controllers have been proposed. In this context, recent research shows that a combination of bank privatization and open-row policy (exploiting the caching over the boundary of a single request) represents an effective way to tackle the problem. However, such approach uncovered a new challenge: the data bus turnaround overhead. In SDRAMs, a single data bus is shared by read and write operations. Alternating read and write operations is, consequently, highly undesirable, as the data bus must remain idle during a turnaround. Therefore, in this article, we propose a SDRAM controller that reorders read and write commands, which minimizes data bus turnarounds. Moreover, we compare our approach analytically and experimentally with existing real-time SDRAM controllers both from the worst-case latency and power consumption perspectives. [ABSTRACT FROM PUBLISHER]

Energy efficiency is a challenging issue in autonomous and distributed sensing systems, especially when these systems are powered by renewable energy sources. In this paper, we present a link and energy adaptive UWB-based sensing technique to improve the detection time coverage and detection range coverage for self-sustained embedded applications. The basic idea is derived from the fact that domain-specific information in such applications is often available. Thus, by jointly exploiting the link information between the transmitter and receiver of the UWB pulse radar, and the non-deterministic characteristics of the renewable energy, the proposed technique dynamically adjusts the pulse repetition frequency of the UWB radar to enhance the sustainable operation under the unreliable energy supply. The overhead of the proposed technique is negligible as compared with the overall energy consumption of the UWB pulse radar. It was demonstrated that the proposed technique can achieve much better detection time coverage and detection range coverage than the conventional UWB radar. The proposed technique is also insensitive to many practical issues such as the limited battery capacity. [ABSTRACT FROM AUTHOR]

Embedded systems consist of one or more processing units which are completely encapsulated by the devices under their control, and they often have stringent timing constraints associated with their functional specification. Previous research has considered the performance of different types of task scheduling algorithm and developed associated timing analysis techniques for such systems. Although preemptive scheduling techniques have traditionally been favored, rapid increases in processor speeds combined with improved insights into the behavior of non-preemptive scheduling techniques have seen an increased interest in their use for real-time applications such as multimedia, automation and control. However when non-preemptive scheduling techniques are employed there is a potential lack of error confinement should any timing errors occur in individual software tasks. In this paper, the focus is upon adding fault tolerance in systems using non-preemptive deadline-driven scheduling. Schedulability conditions are derived for fault-tolerant periodic and sporadic task sets experiencing bounded error arrivals under non-preemptive deadline scheduling. A timing analysis algorithm is presented based upon these conditions and its run-time properties are studied. Computational experiments show it to be highly efficient in terms of run-time complexity and competitive ratio when compared to previous approaches. [ABSTRACT FROM AUTHOR]

Multi-Processor Systems-on-Chip (MPSoCs) have emerged as an evolution trend to meet the growing complexity of embedded applications with increasing computation parallelism. Particularly, real-time applications make out a significant portion of the embedded field. Networks-on-Chip (NoCs) are the backbone of communications in an MPSoC platform. However, the use of NoCs in real-time systems imposes complex constraints on the overall design. This paper discusses the challenges faced, when designing NoCs for real-time applications. Contributions in this area are surveyed on the level of guaranteed Quality-of-Service (QoS) support, adaptivity, and energy efficient techniques. Furthermore, the evaluation methodologies and experimental performance measurements of real-time NoCs are examined. This survey provides a comprehensive overview of existing endeavors in real-time NoCs and gives an insight towards future promising research points in this field. [ABSTRACT FROM AUTHOR]

Multi-core processors are increasingly popular because they yield higher performance, but they also present new challenges for hard real-time systems in that they make it much more difficult to estimate a task's worst-case execution time (WCET). Partitioned cache architecture is being used to ease the problem by providing an isolated execution environment for each thread. Although simple to implement and use, this method may be sub-optimal with respect to both energy consumption and performance since it prevents taking advantage of information shared across threads for both instructions and data. This work presents a new cache architecture termed SPACE (Semi-Partitioned CachE) that makes it possible to leverage information sharing, yielding in turn a tighter WCET. The SPACE architecture together with our new WCET algorithm can be used to maintain the predictability of the execution time of the parallel threads while reducing the overall energy consumption of the system. The new proposed cache architecture was implemented using Verilog and deployed on a Xilinx MicroBlaze multi-core design for testing, validation and measurements. The application level experiments were conducted using the Chronos tool for estimation and the Wattch/SimpleScalar simulator for execution. Using three real-time programs–a radar tracker, a DES encryption algorithm, and an FM radio–we showed that SPACE together with the enhanced WCET algorithm reduce the average system WCET of these applications by 31 percent and reduce the actual energy consumption by 18 percent in comparison with other cache architectures. [ABSTRACT FROM PUBLISHER]

On emerging multicore systems, task replication is a powerful way to achieve high reliability targets. In this paper, we consider the problem of achieving a given reliability target for a set of periodic real-time tasks running on a multicore system with minimum energy consumption. Our framework explicitly takes into account the coverage factor of the fault detection techniques and the negative impact of Dynamic Voltage Scaling (DVS) on the rate of transient faults leading to soft errors. We characterize the subtle interplay between the processing frequency, replication level, reliability, fault coverage, and energy consumption on DVS-enabled multicore systems. We first develop static solutions and then propose dynamic adaptation schemes in order to reduce the concurrent execution of the replicas of a given task and to take advantage of early completions. Our simulation results indicate that through our algorithms, a very broad spectrum of reliability targets can be achieved with minimum energy consumption thanks to the judicious task replication and frequency assignment. [ABSTRACT FROM PUBLISHER]

Computer vision and deep learning are clearly demonstrating a capability to create engaging cognitive applications and services. However, these applications have been mostly confined to powerful Graphic Processing Units (GPUs) or the cloud due to their demanding computational requirements. Cloud processing has obvious bandwidth, energy consumption and privacy issues. The Eyes of Things (EoT) is a powerful and versatile embedded computer vision platform which allows the user to develop artificial vision and deep learning applications that analyse images locally. In this article, we use the deep learning capabilities of an EoT device for a real-life facial informatics application: a doll capable of recognizing emotions, using deep learning techniques, and acting accordingly. The main impact and significance of the presented application is in showing that a toy can now do advanced processing locally, without the need of further computation in the cloud, thus reducing latency and removing most of the ethical issues involved. Finally, the performance of the convolutional neural network developed for that purpose is studied and a pilot was conducted on a panel of 12 children aged between four and ten years old to test the doll.

Real-time safety-critical systems should provide hard bounds on an applications’ performance. SDRAM controllers used in this domain should therefore have a bounded worst-case bandwidth, response time, and power consumption. Existing works on real-time SDRAM controllers only consider a narrow range of memory devices, and do not evaluate how their schedulers’ performance varies across memory generations, nor how the scheduling algorithm influences power usage. The extent to which the number of banks used in parallel to serve a request impacts performance is also unexplored, and hence there are gaps in the tool set of a memory subsystem designer, in terms of both performance analysis, and configuration options. [ABSTRACT FROM AUTHOR]

This paper proposes an N-modular redundancy (NMR) technique with low energy-overhead for hard real-time multi-core systems. NMR is well-suited for multi-core platforms as they provide multiple processing units and low-overhead communication for voting. However, it can impose considerable energy overhead and hence its energy overhead must be controlled, which is the primary consideration of this paper. For this purpose the system operation can be divided into two phases: indispensable phase and on-demand phase. In the indispensable phase only half-plus-one copies for each task are executed. When no fault occurs during this phase, the results must be identical and hence the remaining copies are not required. Otherwise, the remaining copies must be executed in the on-demand phase to perform a complete majority voting. In this paper, for such a two-phase NMR, an energy-management technique is developed where two new concepts have been considered: i) Block-partitioned scheduling that enables parallel task execution during on-demand phase, thereby leaving more slack for energy saving, ii) Pseudo-dynamic slack, that results when a task has no faulty execution during the indispensable phase and hence the time which is reserved for its copies in the on-demand phase is reclaimed for energy saving. The energy-management technique has an off-line part that manages static and pseudo-dynamic slacks at design time and an online part that mainly manages dynamic slacks at run-time. Experimental results show that the proposed NMR technique provides up to 29 percent energy saving and is 6 orders of magnitude higher reliable as compared to a recent previous work. [ABSTRACT FROM PUBLISHER]

Embedded systems are becoming pervasive in diverse domains, but their complexity and heterogeneity calls for new, efficient development methods to ensure their reliability and safety. The authors present a discrete-event modeling and simulation methodology based on solid mathematical theory to deal with these issues. The presented methodology also allows model-checking for verifying design properties. [ABSTRACT FROM AUTHOR]

Task switching, synchronization, and communication between processes are major problems for each real-time operating system. Software implementation of the specific mechanisms may lead to significant delays that can affect deadline requirements for some applications. This paper presents a hardware scheduler architecture integrated into the CPU structure that uses resource remapping techniques for the pipeline registers and for the CPU working registers. We present an original implementation of the hardware structure used for static and dynamic scheduling of the task, unitary management of events, access to architecture shared resources, event generation, and a method used for assigning interrupts to tasks that insures an efficient operation in the context of real-time control. One assembler instruction is used for simultaneous task synchronization with multiple event sources. This architecture allows a task switching time of one clock cycle (with a worst case scenario of three clock cycles for special instructions used for external memory accesses) and a response time of only 1.5 clock cycles for the events. Some mechanisms for improving program execution speed are also taken in consideration. [ABSTRACT FROM AUTHOR]

In high throughput applications, such as in multimedia, it is preferable to fully utilize computing resources, even at the price of some (bounded) delay. However, in real-time systems, where the maximum admissible delay is modeled by a deadline, most of the theory is developed with the assumption of a task deadline smaller than or equal to the task period. The reason of this limitation is in the intrinsic difficulty of the schedulability analysis in the arbitrary deadline case. The most notable guarantee test for sets of arbitrary deadline tasks was due to Lehoczky in 1990. In this paper, we propose the quadratic utilization bound applicable to tasks with arbitrary deadline, which extends Lehoczky’s result. The improvement is made possible by providing some information about the task periods. [ABSTRACT FROM AUTHOR]

Energy consumption is one of the major issues for modern embedded systems. Early, power saving approaches mainly focused on dynamic power dissipation, while neglecting the static (leakage) energy consumption. However, technology improvements resulted in a case where static power dissipation increasingly dominates. Addressing this issue, hardware vendors have equipped modern processors with several sleep states. We propose a set of leakage-aware energy management approaches that reduce the energy consumption of embedded real-time systems while respecting the real-time constraints. Our algorithms are based on the race-to-halt strategy that tends to run the system at top speed with an aim to create long idle intervals, which are used to deploy a sleep state. The effectiveness of our algorithms is illustrated with an extensive set of simulations that show an improvement of up to 8% reduction in energy consumption over existing work at high utilization. The complexity of our algorithms is smaller when compared to state-of-the-art algorithms. We also eliminate assumptions made in the related work that restrict the practical application of the respective algorithms. Moreover, a novel study about the relation between the use of sleep intervals and the number of pre-emptions is also presented utilizing a large set of simulation results, where our algorithms reduce the experienced number of pre-emptions in all cases. Our results show that sleep states in general can save up to 30% of the overall number of pre-emptions when compared to the sleep-agnostic earliest-deadline-first algorithm. [ABSTRACT FROM AUTHOR]

An autonomous fault-tolerant system (AFTS) is one that can reconfigure its own resources in the presence of permanent defects and spontaneous random faults occurring in its silicon substrate in order to maintain the original functionality. This capability makes an AFTS especially suitable for use in harsh environments, where traditional electronics technology is susceptible to failure. This article describes the contributions of the Reliable Reconfigurable Real-Time Operating System (R3TOS) for building an AFTS using currently available Xilinx partially-reconfigurable field-programmable gate arrays. Namely, this article discusses what R3TOS offers for developing durable, dependable, and real-time embedded systems to be used in rugged environments. In this context, the article presents an R3TOS-based inverter controller of a real-world railway traction system that is proven to recover from most of the errors injected without requiring any human intervention. [ABSTRACT FROM PUBLISHER]

A novel method for a mobile phone centric observation of a user’s facing direction is presented. To estimate this direction, our proposed technique exploits the acceleration pattern that can be measured by a smartphone as the user is walking. For an accurate analysis of the acceleration pattern, the proposed approach benefits from a new trigonometric interpolation scheme. Our algorithm is independent of the initial orientation of the device and is adaptable to various wearing positions on a user’s body, which gives the user a larger degree of freedom. A detailed description of the algorithm, which has been customized for a trouser pocket is presented. In addition, complementary hints for adaptation of the algorithm to other wearing positions along with an example of chest pocket position are provided. We have evaluated a prototype implementation of our algorithm on a smartphone, through several field experiments. It has been observed that our algorithm outperforms the conventional GPS and PCA-based techniques in terms of accuracy, reliability and energy consumption. The results also show that our approach has been able to handle the sudden variations of the user’s direction. We have further incorporated our algorithm into a dead-reckoning application as an example of its real-world utility. [ABSTRACT FROM PUBLISHER]

Incremental linear model trees with approximate lookahead are fast, but produce overly large trees. This is due to non-optimal splitting decisions boosted by a possibly unlimited number of examples obtained from a data source. To keep the processing speed high and the tree complexity low, appropriate incremental pruning techniques are needed. In this paper, we introduce a pruning technique for the class of incremental linear model trees with approximate lookahead on stationary data sources. Experimental results show that the advantage of approximate lookahead in terms of processing speed can be further improved by producing much smaller and consequently more explanatory, less memory consuming trees on high-dimensional data. This is done at the expense of only a small increase in prediction error. Additionally, the pruning algorithm can be tuned to either produce less accurate model trees at a much higher processing speed or, alternatively, more accurate trees at the expense of higher processing times. [ABSTRACT FROM PUBLISHER]

This paper investigates the feasibility of real-time scheduling with mobile hypervisor, Xen-ARM. Particularly for mobile virtual machines, real-time support is in high demand. However, it is difficult to guarantee real-time scheduling with virtual machines because inter-VM and intra-VM schedulability have to be determined in multi-OS environments. To address the schedulability, first, this paper presents a definition of a real-time virtual machine. Second, this paper analyzes intra-VM schedulability, taking quantization overhead into account. Quantization overhead comes from tick-based scheduling of Xen-ARM, which requires integer presentation of scheduling period and execution slice. Third, to minimize quantization overhead, this paper provides a new algorithm, called SH-quantization that provides accurate and efficient parameterization of a real-time virtual machine. Fourth, this paper presents an inter-VM schedulability test for incorporating multiple real-time virtual machines. To evaluate the approach, we implement the SH-quantization algorithm in Xen-ARM and paravirtualize a real-time OS, called xeno- \(\mu \) C/OS-II. We ran extensive experiments with various configurations of real-time tasks on a real hardware platform in order to characterize the scheduling behavior of real-time virtual machine with quantization. The results show that quantization overhead consumes additional CPU bandwidth up to 90% and the proposed algorithm guarantees intra/inter-VM schedulability with minimal CPU bandwidth. [ABSTRACT FROM AUTHOR]