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The number of incremental and iterative steps in the digital IC design & automation methodology will decide the non-recurring-engineering (NRE) costs and time-to-market (TTM). Since the aforementioned factors are the major driving factors of the IC design industry, many algorithms were proposed in the last few decades to minimize/optimize the number of design steps in the conventional digital IC design & automation methodology. However, the conventional front end and back end designs have been carried out separately, which has limited the further minimization of design steps. Here we propose a novel digital IC design & automation methodology, which reduces the NRE costs and TTM by merging the front end and back end designs partially. It maps the input RTL description directly to their corresponding physical layouts(derived using the existing CAD tools and stored in a pre-computed library) without going through the all the steps in conventional logic and physical synthesis process. As part of the proposed methodology, we use a pre-computed library which stores all required physical layouts and their Boolean functions. We have exploited the functional symmetry and negation-permutation-negation (NPN) class representations to decoct the library size and number of comparisons. The functional symmetry reduced the number of required pre-computed circuits in our experiments from ] 1031 to 222 (464.4% reduction in the memory size) and helps in maintaining the regularity in the design, which is a major concern for engineering change order.

Pantothenate kinase (PanK) catalyzes the phosphorylation of pantothenate, the first committed and rate-limiting step toward coenzyme A (CoA) biosynthesis. In our earlier reports, we had established that the type I isoform encoded by the coaA gene is an essential pantothenate kinase in Mycobacterium tuberculosis, and this vital information was then exploited to screen large libraries for identification of mechanistically different classes of PanK inhibitors. The present report summarizes the synthesis and expansion efforts to understand the structure-activity relationships leading to the optimization of enzyme inhibition along with antimycobacterial activity. Additionally, we report the progression of two distinct classes of inhibitors, the triazoles, which are ATP competitors, and the biaryl acetic acids, with a mixed mode of inhibition. Cocrystallization studies provided evidence of these inhibitors binding to the enzyme. This was further substantiated with the biaryl acids having MIC against the wild-type M. tuberculosis strain and the subsequent establishment of a target link with an upshift in MIC in a strain overexpressing PanK. On the other hand, the ATP competitors had cellular activity only in a M. tuberculosis knockdown strain with reduced PanK expression levels. Additionally, in vitro and in vivo survival kinetic studies performed with a M. tuberculosis PanK (MtPanK) knockdown strain indicated that the target levels have to be significantly reduced to bring in growth inhibition. The dual approaches employed here thus established the poor vulnerability of PanK in M. tuberculosis.

In this paper, we propose two different algorithms for Shannon Factor Graph (SFG) construction, which can be used for cut-less mapping, to improve the runtime, graph size and required memory size. The first SFG construction algorithm does not consider the nature of the nodes (constant one and zero, non-decomposed and shared nodes) while building the SFG, whereas the second algorithm finds out the nature of the nodes on-the-fly. We observed that the constant one and zero, Shared and non-decomposed nodes can be used at the time of SFG construction to minimize the runtime and graph size significantly and to make the graph semi-canonical. The theoretical analysis and experiments performed on the standard benchmark circuits show that, by finding the constant one and zero, shared and non-decomposed nodes on-the-fly reduces the graph size by a factor of 126 and the runtime by a factor of 5.5.

3-D IC integration technology is recent evolution in IC fabrication which allows reduction of interconnect length, heterogeneous integration of different IC layers ...etc. But one of the challenges faced by 3-D IC is heat mitigation. Over the years to relieve the heating problem in 3-D ICs various passive cooling techniques were proposed. However due to their passive nature, performance is already saturated. So a new technique is proposed to overcome this limitation, called as active cooling technique. This technique uses the Peltier element to mitigate the heat at different IC layers. To demonstrate the advantages of this technique, thermal simulation of a stack consisting of three IC layers bonded face up is performed and extensive case studies are carried out using finite element modeling. It has been observed that by inserting an electrically isolated Peltier element that extends across IC layers to substrate reduced the temperature by ~ 15° K. The initial temperature difference between top IC layer and sink is reduced from ~ 172° K to ~ 16° K i.e a reduction of ~ 90 % compared to ~ 61.7 % with TTSV.

Conventional digital IC computer-aided design (CAD) and automation flow incorporates hierarchical methodology following the Gajski Chart. Such methodology uses separate front end and backend CAD tools in complex and incremental steps, incurring increased design time and higher non-recurring engineering (NRE) costs. In this paper, we propose a novel and unified methodology merging the front end and backend without requiring the front end CAD tool usage. Moreover, the complexity of hierarchical design steps is drastically reduced by mapping the input register-transfer level (RTL) description directly to their corresponding physical designs, derived using the existing CAD tools and stored in pre-computed technology libraries. To reduce the size and storage of these libraries, negation-permutation-negation (NPN) classes have been used throughout. As a result, our proposed methodology offers advantages in terms of significantly reduced NRE costs and time-to-market. To demonstrate these advantages, extensive case studies have been carried out using benchmark circuits. Our experimental results and analysis show that these advantages achieved without limiting our methodology to number of input variables in a function using precomputed technology libraries with 1030 circuits only

RE costs and Time-to-Market are the two contributing factors in current IC industries to keep up with the competition with the embedded systems market. To reduce both is a challenge to the research community to come up with a design automation solution. Here, we propose a Design Automation methodology by introducing the concept of Dynamic Library Concept. The methodology uses the libraries of the layouts of the already designed blocks for the later use in further designs. Thereby, reducing the design time and cost associated with it. Here, we are presenting the preliminary findings by considering the standard full adder and 4-Bit adder examples