30 results on '"Repossi, Matteo"'
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2. Planar models of reconfigurable MEMS circuits
3. Multi-Rate Low-Noise Optical Receiver Front-End
4. Design and Optimization of Integrated Transmission Lines on Scaled CMOS Technologies
5. 12.2 A 4-Channel 200Gb/s PAM-4 BiCMOS Transceiver with Silicon Photonics Front-Ends for Gigabit Ethernet Applications
6. A 26-Gb/s 3-D-Integrated Silicon Photonic Receiver in BiCMOS-55 nm and PIC25G With – 15.2-dBm OMA Sensitivity
7. A 26-Gb/s 3-D-Integrated Silicon Photonic Receiver in BiCMOS-55 nm and PIC25G With −15.2-dBm OMA Sensitivity
8. High Capacity Silicon Photonics Packaging
9. Demonstration of a Partially Integrated Silicon Photonics ONU in a Self-Coherent Reflective FDMA PON
10. Insights Into Silicon Photonics Mach–Zehnder-Based Optical Transmitter Architectures
11. Transmitter Made up of a Silicon Photonic IC and its Flip-Chipped CMOS IC Driver Targeting Implementation in FDMA-PON
12. A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links
13. A fully packaged 25 Gbps/channel WDM photoreceiver module based on a Silicon Photonic Integrated Circuit and a flip-chipped CMOS quad transimpedance amplifier
14. 23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies
15. 22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s
16. A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies
17. A Low-Noise Design Technique for High-Speed CMOS Optical Receivers
18. A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4
19. A 5mW CMOS wideband mm-wave front-end featuring 17dB of conversion gain and 6.5 dB minimum NF
20. A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS
21. A 24 GHz Subharmonic Direct Conversion Receiver in 65 nm CMOS
22. A 60GHz receiver with 13GHz bandwidth for Gbit/s wireless links in 65nm CMOS
23. A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization
24. A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators
25. Design of Low-Loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations
26. Analysis of loss mechanisms in coplanar waveguides integrated on bulk CMOS substrates
27. A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication
28. A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS
29. A Magnetically Tuned Quadrature Oscillator
30. A 3.2-to-7.3GHz Quadrature Oscillator with Magnetic Tuning
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