1. 62.5 ps LSB resolution multiphase clock Time to Digital Converter (TDC) implemented on FPGA
- Author
-
Mahantesh P Mattada and Hansraj Guhilot
- Subjects
Environmental Engineering ,Computer science ,020209 energy ,General Chemical Engineering ,0211 other engineering and technologies ,02 engineering and technology ,Network topology ,Catalysis ,Time-to-digital converter ,Least significant bit ,021105 building & construction ,Hardware_INTEGRATEDCIRCUITS ,0202 electrical engineering, electronic engineering, information engineering ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Electrical and Electronic Engineering ,Field-programmable gate array ,Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION ,Civil and Structural Engineering ,Virtex ,business.industry ,Mechanical Engineering ,Resolution (electron density) ,General Engineering ,Phase-locked loop ,Clock time ,business ,Computer hardware - Abstract
A 13-bit Time to Digital Converter is implemented using multiphase clock technique. Xilinx’s Virtex 5 FPGA platform is used to realize the TDC architecture. One PLL within the FPGA works as a clock synthesizer to multiply the reference clock to 500 MHz. Then the combination of PLL and DLL topologies are used to generate 16 phases of the clock, separated by 11.25°. Further, 16 phases are generated by inverting the first 16 phases. A resolution of 62.5 ps has been recorded. Measured INL and DNL are within 1 LSB. The present work is suitable for many critical applications due to its PVT insensitive and robust properties.
- Published
- 2022