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In this paper, using calibrated TCAD simulations, we demonstrate how the performance of a Tunneling FET (TFET) can be improved by using a new phenomenon called drain induced barrier widening (DIBW) at the source-channel junction. Our results indicate that TFETs in which DIBW dominates exhibit a steep subthreshold swing (≈35 mV/dec) and a low OFF-state current ( $\approx 10^{-16}\text{A}/\mu \text{m}$ ) without affecting the ON-state current. We also show that TFETs exhibit a reverse short channel effect due to an increase in the tunneling width at the source-channel junction.

In this article, we analyze the issue of gate-induced-drain-leakage (GIDL) in metal-ferroelectric-insulator-semiconductor (MFIS)-type negative capacitance fin field-effect transistor (NC-FinFET) using 3-D technology computer-aided design (TCAD) simulations. We present a comprehensive analysis of GIDL characteristics on 7-nm technology node with respect to the variation of ferroelectric and silicon body thicknesses, source/drain junction placement, and source/drain doping concentration of NC-FinFET. We find that in NCFET, steeper energy band profiles near the source and drain side caused by fringing field coupling to the ferroelectric result in a prior and larger onset of the longitudinal band to band tunneling (L-BTBT) current compared to the baseline FinFET. Also, we find that, unlike the conventional FinFET, NC-FinFET shows the nonmonotonic trend in the occurrence of the L-BTBT component as we scale down the channel length of the device due to the reverse short channel effect.

A digital cell library operating in the near-threshold voltage (NTV) region is presented to obtain both high energy efficiency and optimized performance. The proposed library oriented to the NTV region is optimized using the parasitic effects of nanometer process technology and a body-biasing technique. To maximize the energy efficiency, the proposed cell library utilized the minimum width allowed by the process as the base width unit. To enhance the performance, digital cells were developed with various strengths whose sizing method relies on the minimum unit width, reverse short channel effect, and inverse narrow width effect. An asymmetric gate-length scheme is applied to multi-fan-in logic gates to increase the performance. Also, the proposed TAP cell was added, combined with an inverter-based forward body-biasing circuit. Finally, a library with 59 cells was developed and made available for synthesis and automatic layout and the proposed NTV library was then evaluated with ISCAS benchmark logics. The proposed NTV cell library shows more than 10~20% less energy consumption compared with a conventional digital cell library using minimum gate length and monolithic width. EDP is also increased by 10~20% with a simply controlled body-biasing scheme compared with the conventional one.

In this study, we investigate threshold voltage (VTH) variability of metal-oxide-semiconductor field-effect transistors induced by random dopant fluctuation (RDF). Our simulation work demonstrates not only the influence of the implantation parameters such as its dose, tilt angle, energy, and rotation angle on the RDF-induced VTH variability, but also the solution to reduce the effect of this variability. By adjusting the ion implantation parameters, the 3σ (VTH) is reduced from 43.8 mV to 28.9 mV. This 34% reduction is significant, considering that our technique is very cost effective and facilitates easy fabrication, increasing availability.

The paper reports the analytical model for the analysis of the effects of channel doping on the threshold voltage. A silicon germanium p-MOSFET with high-k dielectric material along with a metal gate is used for the analysis. The presented model considers the short channel effects, junction depth, doping of the layers and metal gate work function. Results are validated with the 22 nm device geometry. The MOSFET with reduced channel doping reflects the corresponding reduction in the threshold voltage. The model can effectively analyze the SiGe p-MOSFET for device designing in the nanometer regime.

An all-region short-channel MOSFET, model is developed for nanowire semiconductors with 1-D density of states. It is shown that in the quantum capacitance limit, the long-channel saturation current exhibits a ( Vgs − Vt )3/2 dependence on gate voltage. With the velocity saturation effect implemented in the model, the Ids – Vgs characteristics of 1-D MOSFETs are compared to those of 2-D MOSFETs at 10-nm channel length. The above threshold model is joined with a subthreshold current model derived from short-channel solutions to form an I – V model continuous in all regions.

This paper proposes how to experimentally define the threshold voltage for various TFETs based on the theoretical point of view. We propose that the gate voltage defined corresponding to the peak of normalized transconductance is effectively the threshold voltage of TFETs. We also demonstrate that this definition is valid for different structures of TFET. In addition, we address the short-channel effect with such definition of threshold voltage for lateral TFET. It is shown that the short-channel effect significantly increased the off-current and the threshold voltage due to the extension of the drain potential and degradation of gate-field integrity in TFETs.

A two-dimensional analytical model for the surface potential and threshold voltage of a dual work function Schottky barrier (SB) MOSFET is presented. The developed model considers the effects of the varying gate metal work function, gate and drain voltages, and different doping concentrations, gate dielectric permittivity, and silicon thickness. For solving the electrostatic potential of the SB-MOSFET by using Poisson’s equation with appropriate boundary conditions, parabolic approximation has been considered. The proposed device has also incorporated the effect of barrier height lowering at the metal/semiconductor contacts. The results of our modeled surface potential and the threshold voltage, match with technology computer aided design simulations.

The peak switching currents of two paralleled MOSFETs turned on/off by one gate driver could differ significantly owing to the mismatch in threshold voltages (Vth). The passive balancing method described herein employs one inductor and one resistor per MOSFET to force the currents to track with negligible penalty in loss. Sensors, feedbacks, and knowledge of gate-related parameters (such as gate charge, polarity of Vth difference, gate impedances, etc.) are not required. The passive components are designed using an inequality involving Vth, rise time, and unbalance percentage. The mismatch in peak currents is reduced from 15% to 1% between SiC MOSFETs tested at 20 A and 300 V with 19% Vth variation.

In this paper, a 2-D analytical model for surface potential and threshold voltage of novel vertical super-thin body (VSTB) FET has been derived by solving 2-D Poisson equation. The analytical surface potential expression for gate-side surface and sidewall side surface has been modeled using parabolic surface potential approximation. The threshold voltage model for the VSTB FET has been derived by applying strong inversion criterion at the surface potential minimum value. The threshold voltage model for the VSTB FET has been analyzed by varying the body thickness, oxide thickness, and channel doping concentrations. The drain-induced barrier lowering and threshold voltage roll-off parameters are also extracted and analyzed for different body thicknesses. The models for surface potential and threshold voltage have been compared with the results obtained from the 2-D numerical device simulator and a very good agreement between the two has been observed.

An alternative method for an extraction of the MOSFET threshold voltage has been proposed. It is based on an analysis of the MOSFET source-bulk junction capacitance behavior as a function of the gate-source voltage. The effect of the channel current on the threshold voltage extraction is fully eliminated. For the threshold voltage and junction capacitance model parameters non-iterative methods have been used. The proposed method has been demonstrated using a series of MOS transistors manufactured using a standard CMOS technology.

In this paper, a 2D compact model for potential and threshold voltage for lightly doped symmetrical double gate (DG) p-channel MOSFETs (PMOS) including negative bias temperature instability (NBTI) and short channel effects (SCEs) is presented. The model is dedicated to nano scale MOSFETs below 30 nm. In this model, both effects of interface state generation and hole-trapping are considered. Moreover, the effects of scaling down the oxide thickness and the channel thickness on NBTI are discussed. Our model is matched very well with numerical simulations obtained from COMSOL multi-physics at different drain voltages (Vd). A 4% shift in threshold voltage roll-off and 47% shift in drain induced barrier lowering (DIBL) is achieved at a gate length of 10 nm after 10 years of operation at a frequency of 1 GHz.

Two dimensional threshold voltage model of ion-implanted strained-Si double-material double-gate MOSFETs has been done based on the solution of two dimensional Poisson’s equation in the channel region using the parabolic approximation method. Novelty of the proposed device structure lies in the amalgamation of the advantages of both the strained-Si channel and double-material double-gate structure with a vertical Gaussian-like doping profile. The effects of different device parameters (such as device channel length, gate length ratios, germanium mole fraction) and doping parameters (such as projected range, straggle parameter) on threshold voltage of the proposed structure have been investigated. It is observed that the subthreshold performance of the device can be improved by simply controlling the doping parameters while maintaining other device parameters constant. The modeling results show a good agreement with the numerical simulation data obtained by using ATLAS™, a 2D device simulator from SILVACO.

This paper analyzes the influence of tunneling current on threshold voltage shift by channel length of short channel asymmetric double gate(DG) MOSFET. Tunneling current significantly increases by decrease of channel length in the region of 10 nm below, and the secondary effects such as threshold voltage shift occurs. Threshold voltage shift due to tunneling current is not negligible even in case of asymmetric DGMOSFET to develop for reduction of short channel effects. Off current consists of thermionic and tunneling current, and the ratio of tunneling current is increasing with reduction of channel length. The WKB(Wentzel-Kramers-Brillouin) approximation is used to obtain tunneling current, and potential distribution in channel is hermeneutically derived. As a result, threshold voltage shift due to tunneling current is greatly occurred for decreasing of channel length in short channel asymmetric DGMOSFET. Threshold voltage is changing according to bottom gate voltages, but threshold voltage shifts is nearly constant.

This paper presents an analytical threshold voltage model for back-gated fully depleted (FD), recessed-source drain silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs). Analytical surface potential models have been developed at front and back surfaces of the channel by solving the two-dimensional (2-D) Poisson’s equation in the channel region with appropriate boundary conditions assuming a parabolic potential profile in the transverse direction of the channel. The strong inversion criterion is applied to the front surface potential as well as on the back one in order to find two separate threshold voltages for front and back channels of the device, respectively. The device threshold voltage has been assumed to be associated with the surface that offers a lower threshold voltage. The developed model was analyzed extensively for a variety of device geometry parameters like the oxide and silicon channel thicknesses, the thickness of the source/drain extension in the buried oxide, and the applied bias voltages with back-gate control. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained from ATLAS™, a 2-D device simulator from SILVACO.

The effect of Al doping concentration (NA) at channel regions ranging from 1.0×1017 to 4.0×1017 cm-3 on the effective channel mobility of electron (μeff) and the threshold voltage (Vth) instability under the positive bias-temperature-stress conditions has been investigated througu the use of trench-gate 4H-SiC MOSFETs with m-face (1-100) channel regions. It was found that μeff degraded with an increase in NA. On the other hand, the increase of NA enlarged the Vth instability. These results indicate that NA has a large impact not only on the Vth value but also on the channel resistance and reliability in 4H-SiC trench MOSFETs.

We study the threshold voltage (Vth) instability of commercially available silicon carbide (SiC) power MOSFETs or prototypes from four different manufacturers under positive bias temperature stress (PBTS). A positive bias near the Vth causes a threshold voltage shift of 0.7 mV per decade in time per nanometer oxide thickness in the temperature range between-50 °C and 150 °C. Recovery at +5 V after a 100 s +25 V gate-pulse causes a recovery between-1.5 mV/dec/nm and-1.0 mV/dec/nm at room temperature and is decreasing with temperature. All devices show similar stress, recovery and temperature dependent behavior indicating that the observed Vth instabilities are likely a fundamental physical property of the SiC-SiO2 system caused by electron trapping in near interface traps. It is important to note that the trapping is not causing permanent damage to the interface like H-bond-breakage in silicon based devices and is nearly fully reversible via a negative gate bias.

Boron transient enhanced diffusion (TED) causes reverse short channel effect, and threshold voltage (Vt) increases abnormally, which seriously affects the device performance and yield. The Vt increment is different with different channel size. To investigate channel impurity distribution and the influence of channel size on TED, Vt adjustment ion-implantation, LDD ion-implantation and carbon co-implantation experiments were performed on 40 nm CMOS process, measuring Vt with different channel size and process, and using TCAD tools for process simulation. Experiments results show that Vt rises first with channel length decreasing and then drops sharply after reaching the maximum at 0.55 μm. The Vt -L curve slope decreases when channel width decreases. Vt decreases with channel width and it is decreasing faster and faster when channel length is constant. The interstitial Si atoms are injected by LDD ion-implantation and diffuse into channel, while boron pile up at the LDD-channel boundary. However, boron leak into the shallow trench isolation (STI) area at the corner formed by LDD and channel. Both pile-up and leakage control boron concentration distribution in channel. The Vt shift induced by boron TED is channel size-dependent, and high energy carbon co-implantation and infrared rapid thermal anneal can suppress TED effect effectively.

The modulation of equivalent channel mobility μ eq can fit the accurate drain current in high accuracy as the change of horizontal electrical field, related to the drain bias and the channel length with fixed gate bias. The fitting I-V curves contain long, middle and short-channel devices. In this model, the short channel effect, reverse short channel effect, DIBL are taken into consideration to satisfying the whole reliable drive current model.

A circuit operating at near-threshold voltage (NTV) dissipates much less energy, but it suffers from significant increase in cell delay as well as delay variation. In this paper, we address two library optimization methods for NTV design: (1) transistor lengths are increased to benefit from reverse short channel effect (RSCE), and (2) each flip-flop is optimized into a few versions with different timing parameters by redistributing clock signals to clocked transistors. Flip-flops are remapped to optimized ones via integer linear programming (ILP); a goal is to minimize total negative slack (TNS) under hold time constraints, which is a critical concern in NTV design. Experiments demonstrate that our proposed method achieves 22%, 56%, and 13% reductions in clock period, energy dissipation, and circuit area, respectively, on average of a few test circuits in 55-nm technology.

In this paper, a three-dimensional 3D model of threshold voltage is presented for dual-metal quadruple-gate metal-oxide-semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge Qinv at the 'virtual-cathode' reaches to a critical charge Qth. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross-section, oxide thickness, and gate length ratio. Further, the drain-induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.

In this paper, we have analyzed the effect of chiral vector, temperature, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage a CNTFET provides over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector pair in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime.

In this work, we investigated the methods that measure the threshold voltage (Vth) instability without relaxation of the gate stress during the Vth measurement. We propose a non-relaxation method that demonstrates exact Vth shifts compared with conventional methods that are not as accurate. In the non-relaxation method, the constant gate-source voltage (Vgs) is continuously applied as a gate stress while the drain voltage (Vds) shift required to maintain a constant drain current (Id) is measured. Then, the Vds shift is converted to a Vth shift. The Vth shift values measured by the non-relaxation method are larger than those measured by the other methods, which means that the non-relaxation method can very accurately measure the Vth shift.

With the effects of equivalent oxide charges on the flat-band voltage, a new quasi-three-dimensional (quasi-3-D) compact threshold voltage model is presented for the pi-gate (ΠG) MOSFETs with the interface trapped charges based on the quasi-3-D scaling equation that accounts for equivalent number of gates and virtual back gate effects induced by the normalized gate extension depth in the buried oxide. The model reveals that a thin gate oxide can effectively reduce the threshold voltage degradation caused by the trapped charges. Opposite to the thin gate oxide, a thick silicon is required to alleviate the threshold voltage shift resulted from the negative trapped charges. For the short-channel behavior, the device with negative/positive trapped charges can decrease/increase the threshold voltage roll-off caused by the short-channel effects. Due to its computational efficiency and simple formula, the model can be easily used to explore the threshold behavior for the charges trapping ΠG MOSFETs.

This paper has analyzed threshold voltage shift for doping profile of asymmetric double gate(DG) MOSFET. Ion implantation is usually used in process of doping for semiconductor device and doping profile becomes Gaussian distribution. Gaussian distribution function is changed for projected range and standard projected deviation, and influenced on transport characteristics. Therefore, doping profile in channel of asymmetric DGMOSFET is affected in threshold voltage. Threshold voltage is minimum gate voltage to operate transistor, and defined as top gate voltage when drain current is  per unit width. The analytical potential distribution of series form is derived from Poisson’s equation to obtain threshold voltage. As a result, threshold voltage is greatly changed by doping profile in high doping range, and the shift of threshold voltage due to projected range and standard projected deviation significantly appears for bottom gate voltage in the region of high doping concentration.

MOSFETs have always been the workhorse of semiconductor industry, with passing decades the sizes of MOSFETs have been continuously decreasing. This is guided by decrease in the gate length or channel length. However decrease in channel length of planar MOSFETs has reached its saturation level due to short channel effects and DIBL. In this paper we have tried to present an electrical comparison between 32nm node technology and 20nm node technology of planar MOS structures. The structures have been fabricated using SILVACO TCAD software and study of threshold voltages and corresponding oxide thickness has been made.

Carbon nanotubes have some unique features and special properties that offer a great potential for nano-electronic devices. In this paper, we have analyzed the effect of chiral vector, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage of CNTFET over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as of MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime especially when the gate length is around 10 nm; which is quite contrary to the well known short channel effects in MOSFET. It is observed that at or below 10 nm channel length the threshold voltage increases rapidly in case of CNTFET device whereas in case of MOSFET device the threshold voltage decreases drastically.

An analytical and scalable model for the threshold voltage in FinFETs has been developed by solving the 3-D Poisson equation using appropriate techniques. The model is also based on a physical analysis of the conduction path. The mobile charge term was considered in the 3-D Poisson's equation to be solved. The threshold voltage is defined as the gate voltage to obtain a certain threshold charge density. Due to its 3-D basis, the model inherently accounts for short-channel effects, such as the threshold voltage roll-off and the Drain Induced Barrier Lowering effect. A very good agreement with 3-D numerical simulations has been observed.

Threshold voltage instability was investigated for 4H-SiC MOSFETs with phosphorus-doped (POCl3-annealed) and nitrided (NO-annealed) gate oxides. Threshold voltage shift observed in the bidirectional drain current–gate voltage characteristics was evaluated using various gate voltage sweeps at room and elevated temperatures up to 200 °C. The threshold voltage shift was also studied after applying positive and negative bias-temperature stress. Two types of MOSFETs showed different instability characteristics, depending on gate biases and temperatures. These features were found to originate from the difference in trap density and trap location at/near the oxide/SiC interface and in the oxide. It is apparent that the oxide traps in phosphorus-doped oxides and near-interface traps in nitrided oxides are the main origin of the threshold voltage instability via capture and emission (in the case of oxide traps, only capture) of both electrons and holes.

This paper discusses the mechanisms that may underlie the short-channel effects of the lateral double-gate tunnel FET. Simulations suggest that the short-channel effect of the threshold voltage is triggered by degradation in the electrostatic integrity of the gate field.

This paper provides detailed comparison of electrical characteristics of accumulation mode and inversion mode 1.2 kV SiC MOSFETs, including performance at high temperatures (up to 200 °C). Statistical data measured from over 50 dies on 6-inch SiC wafers was used for this comparison. It is concluded that the accumulation mode SiC MOSFET provides a lower specific on-resistance than the inversion mode MOSFET due to a higher channel mobility (∼ 22 cm2/V·s) while achieving a reasonable threshold voltage (∼ 2.3 V). Based on statistical data analyses, a strong correlation between the threshold voltage and the field effect channel mobility was identified.

Threshold voltage is an important parameter in case of device modelling. Variation of threshold voltage affects significantly the modelling of a device specially in case of short channel MOSFET. Variation of threshold voltage also affects the analysis of circuits. Threshold voltage depends on different parameters like doping concentration, surface potential, channel length, oxide thickness, temperature etc. Threshold voltage also depends on random dopant fluctuation. In wide planar transistors the threshold voltage is essentially independent of the drain-source voltage and is therefore a well defined characteristic, however it is less clear in modern nanometer-sized MOSFETs due to drain induced barrier lowering. Survey of different literatures on device modelling shows the necessity of the study of the variation of the threshold voltage with the doping concentration, channel length and oxide thickness. Here the variation of the threshold voltage has been studied through empirical formula and graphically.

This paper has analyzed the change of threshold voltage for oxide structure of symmetric and asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET can be fabricated with different top and bottom gate oxide thickness, while the symmetric DGMOSFET has the same top and bottom gate oxide thickness. Therefore optimum threshold voltage is considered for top and bottom gate oxide thickness of asymmetric DGMOSFET, compared with the threshold voltage of symmetric DGMOSFET. To obtain the threshold voltage, the analytical potential distribution is derived from Possion’s equation, and Gaussian distribution function is used as doping profile. We investigate for bottom gate voltage, channel length and thickness, and doping concentration how top and bottom gate oxide thickness influences on threshold voltage using this threshold voltage model. As a result, threshold voltage is greatly changed for oxide thickness, and we know the changing trend greatly differs with bottom gate voltage, channel length and thickness, and doping concentration.

This paper has analyzed threshold voltage movement for channel doping concentration of asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET is generally fabricated with low doping channel and fully depleted under operation. Since impurity scattering is lessened, asymmetric DGMOSFET has the adventage that high speed operation is possible. The threshold voltage movement, one of short channel effects necessarily occurred in fine devices, is investigated for the change of channel doping concentration in asymmetric DGMOSFET. The analytical potential distribution of series form is derived from Possion’s equation to obtain threshold voltage. The movement of threshold voltage is investigated for channel doping concentration with parameters of channel length, channel thickness, oxide thickness, and doping profiles. As a result, threshold voltage increases with increase of doping concentration, and that decreases with decrease of channel length. Threshold voltage increases with decrease of channel thickness and bottom gate voltage. Lastly threshold voltage increases with decrease of oxide thickness.

High-i¾? gate-all-around structure counters the Short Channel Effect SCEs mostly providing excellent off-state performance, whereas high mobility III-V channel ensures better on-state performance, rendering III-V nanowire GAAFET a potential candidate for replacing the current FinFETs in microchips. In this paper, a 2D simulator for the III-V GAAFET based on self-consistent solution of Schrodinger-Poisson equation is proposed. Using this simulator, capacitance-voltage profile and threshold voltage are characterized, which reveal that gate dielectric constant i¾? and oxide thickness do not affect threshold voltage significantly at lower channel doping. Moreover, change in alloy composition of InxGa1-xAs, channel doping, and cross-sectional area has trivial effects on the inversion capacitance although threshold voltage can be shifted by the former two. Although, channel material also affects the threshold voltage, most sharp change in threshold voltage is observed with change in fin width of the channel 0.005V/nm for above 10nm fin width and 0.064V/nm for sub-10nm fin width. Simulation suggests that for lower channel doping below 1023m-3, fin width variation affects the threshold voltage most. Whereas when the doping is higher than 1023m-3, both the thickness and dielectric constant of the oxide material have strong effects on threshold voltage 0.05V/nm oxide thickness and 0.01V/per unit change in i¾?. Copyright © 2014 John Wiley & Sons, Ltd.

We present a temperature dependent model for the threshold voltage Vt and subthreshold slope S of strained-Si channel MOSFETs and validate it with reported experimental data for a wide range of temperature, channel doping concentration, oxide thickness and strain value. Such model includes the effect of lattice strain on material, temperature dependent effective mass of carriers, interface-trapped charge density and bandgap narrowing due to heavy channel doping. Also considered are polydepletion effects, carrier localization effect in the ultra-thin channel and quantum-mechanical effects. Our investigation reveals that the threshold voltage reduces linearly with increasing temperature whereas the subthreshold slope increases. In addition Vt is found to be sensitive to strain while S is weakly dependent on strain. Moreover, the channel doping concentration influences both Vt and S, and also the rate of change of Vt with temperature. Furthermore, S decreases for a lightly doped channel particularly at lower temperatures.

We have investigated the electrical performance of amorphous indium–gallium–zinc oxide (α-IGZO) thin-film transistors with various channel thicknesses. It is observed that when the α-IGZO thickness increases, the threshold voltage decreases as reported at other researches. The intrinsic field-effect mobility as high as 11.1 cm 2 /Vs and sub threshold slope as low as ∼0.2 V/decade are independent on the thickness of α-IGZO channel, which indicate the excellent interface between α-IGZO and atomic layer deposited Al 2 O 3 dielectric even for the case with α-IGZO thickness as thin as 10 nm. However, the source and drain series resistances increased with increasing of α-IGZO channel thickness, which results in the apparent field-effect mobility decreasing. The threshold voltage shift (Δ V th ) under negative bias stress (NBS) and negative bias illumination stress (NBIS) were investigated, also. The hump-effect in the sub threshold region under NBS and threshold voltage shift to negative position under NBIS were enhanced with decreasing of α-IGZO channel thickness, owing to the enhancement of vertical electrical field in channel.

This paper has analyzed threshold voltage roll-off for bottom gate voltages of asymmetric double gate(DG) MOSFET. Since the asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates, the bottom gate voltage influences on threshold voltage. It is , therefore, investigated how the threshold voltage roll-off known as short channel effects is reduced with bottom gate voltage. In the pursuit of this purpose, off-current model is presented in the subthreshold region, and the threshold voltage roll-off is observed for channel length and thickness with a parameter of bottom gate voltage as threshold voltage is defined by top gate voltage that off-currnt is    per channel width. As a result to observe the threshold voltage roll-off for bottom gate voltage using this model, we know the bottom gate voltage greatly influences on threshold voltage roll-off voltages, especially in the region of short channel length and thickness. 키워드 : 비대칭 이중게이트 MOSFET, 문턱전압이동, 하단 게이트 전압, 단채널효과 Key word : asymmetric DGMOSFET, threshold voltage roll-off, bottom gate voltage, short channel effect Journal of the Korea Institute of Information and Communication Engineering 하단게이트 전압에 따른 비대칭 이중게이트 MOSFET의 문턱전압이동 의존성

Continued scaling of transistor has resulted in severe short channel effects and transport degradation. In addition, variability in deeply scaled transistor such as threshold voltage ( V TH ) variability has emerged as a major challenge for circuit and device design. Although various techniques have been suggested to alleviate these problems, such as CMOS on FDSOI or 3D transistors, they are expensive and complicated to manufacture. Recently, MOSFETs with deeply retrograde channel profile have been suggested as a mean to obtain good device characteristics on bulk substrate. In this work, V TH variability impact of RDF on 65 nm-node deeply retrograde MOSFETs and conventional planar bulk MOSFETs were studied by using TCAD simulation. The simulated results showed that the deeply retrograde MOSFETs have 5 mV lower σ-V TH (ΔA VT between two devices is 1.06 mV·μm) than conventional planar bulk MOSFETs at the same I off level (0.2 nA/μm). The ideal BOX profile structure simulated results showed that the thinner the low doping surface layer for deeply retrograde MOSFETs, the higher the V TH variability. Our finding suggest that deeply retrograde MOSFETs are inherently less sensitive to V TH variability due to RDF and channel length than conventional planar bulk MOSFETs and can be feasible for post-CMOS technology.

In the proposed work analytical modeling of single halo triple material surrounding gate (SH-TMSG) MOSFET is developed. The threshold voltage and subthreshold current has been derived using parabolic approximation method and the simulation results are analyzed. The threshold voltage roll off is reduced and it denotes the deterioration of short channel effects. The results of the analytical model are delineated and compared with MEDICI simulation results and it is well corroborated.

With the effects of interface trapped charges on the flat-band voltage, we report a novel quasi-3-D interface-trapped-charge-induced threshold voltage model for quadruple-gate (QG) MOSFETs based on the scaling equation including equivalent number of gates. It is found that a thin gate oxide and a small ratio of damaged region to channel region are required to reduce the threshold voltage degradation by the trapped charges. In addition, the damaged device with a thick silicon film suffers the small threshold voltage degradation by the negative trapped charges. In comparison with other multiple-gate MOSFETs, the QG MOSFET is better than double-gate and triple-gate MOSFETs in suppressing the threshold voltage degradation by the positive trapped charges. The model can be used to explore the hot-carrier-induced threshold voltage of the QG MOSFET for its memory device application.

A new mismatch model of temperature and narrow channel dependence on threshold voltage of MOSFETs and the parameter extraction method are proposed. A new model is developed from spice level3 and BSIM3 model. The IDS -VGS in linear region was used with a different of channel width. The threshold voltage parameters extraction procedure is based on the measurement of the tranconductance characteristics of MOSFET in linear region. In this predicted model, the temperature coefficient for threshold voltage and the body-bias coefficient of threshold voltage of a big MOSFET at various narrow channel width of MOSFET are determined. The results show that the deviations of experimentally measured threshold voltages of both devices from the predicted model are around 3%.

In high-κ/metal-gate (HK/MG) metaloxide-semiconductor field-effect transistors (MOSFETs) at 45-nm and below, the metal-gate material consists of a number of grains with different grain orientations. Thus, Monte Carlo (MC) simulation of the threshold voltage (VTH) variation caused by the workfunction variation (WFV) using a limited number of samples (i.e., approximately a few hundreds of samples) would be misleading. It is ideal to run the MC simulation using a statistically significant number of samples (> ~ 106); however, it is expensive in terms of the computing requirement for reasonably estimating the WFV-induced VTH variation in the HK/MG MOSFETs. In this work, a simple matrix model is suggested to implement a computing-inexpensive approach to estimate the WFV-induced VTH variation. The suggested model has been verified by experimental data, and the amount of WFV-induced VTH variation, as well as the VTH lowering is revealed.

We found that threshold voltage (Vth) of a 4H-SiC MOSFET increases drastically by performing low temperature wet oxidation after nitridation in a gate oxide process. The increment of Vth depends on the wet oxidation conditions. Wet oxidation increases the interface trap density (Dit) at deep level of SiC bandgap and decreases positive charge density inside the gate oxide layer. The amount change of the interface traps and the positive charges in the gate oxide makes Vth higher without a decrease in the channel mobility. We improved the trade-off between Vth and effective carrier mobility (μeff) in the MOSFET channel, and realized a low specific on-resistance (Ron,sp) SiC-MOSFET with Vth over 5 V by using the newly developed process.

Threshold voltage (VTH) of SiC-MOSFETs on various crystal faces has been investigated systematically using the same bias-temperature-stress (BTS) conditions. In addition, dependences of gate-oxide-forming process on VTH instability is also discussed. Nitridation treatments such as N2O and NH3 post-oxidation annealing (POA) are effective in stabilization of VTH under both positive-and negative-BTS tests regardless of crystal face. On the other hand, serious VTH instability was confirmed in MOSFETs with gate oxide by pyrogenic oxidation followed by H2 POA.

Ultra-low power design techniques specifically subthreshold designs, play a vital role in Internet of things systems that survive on limited power budget or harvested energy sources. In this paper, the width and length of a transistor operating at subthreshold region are optimized considering the nano-scale effects such as reverse short channel effect and inverse narrow width effect, which improves performance, reduces area, minimizes sensitivity to process variation and reduces energy consumption. A subthreshold standard cell library consisting of 45 standard cells is designed. The physical synthesis of ISCAS′85 benchmark circuits and a floating point unit shows that energy savings in area-mapped design are up to 23% whereas area savings in performance-mapped design are up to 30%. The measurement results from a test chip fabricated in industrial 130 nm technology demonstrate a performance improvement of up to 27%, reduction in delay variability of up to 24% and energy savings of 18%.