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The Super Proton Synchrotron (SPS) Low-level RF (LLRF) system at CERN was completely revamped in 2020. In the old system, the digital signal processing was clocked by a submultiple of the RF. The new system uses a fixed-frequency clock derived from White Rabbit (WR). This triggered the development of an eRTM module for generating very precise clock signals to be fed to the optional RF backplane in MTCA.4 crates. The eRTM14/15 sandwich of modules implements a WR node delivering clock signals with a jitter below 100 fs. WR-clocked RF synthesis inside the FPGA makes it simple to reproduce the RF elsewhere by broadcasting the frequency-tuning words over the WR network itself. These words are received by the WR2RF-VME module and used to produce beam-synchronous signals such as the bunch clock and the revolution tick. This paper explains the general architecture of this new LLRF system, highlighting the role of WR-based synchronization. It then goes on to describe the hardware and gateware designs for both modules, along with their supporting software. A recount of our experience with the deployment of the MTCA.4 platform is also provided., Proceedings of the 18th International Conference on Accelerator and Large Experimental Physics Control Systems, ICALEPCS2021, Shanghai, China

Additional file 1. Alphabetical list of authors of articles included in the review and summary of study design and findings.

The CERN control system is comprised of multiple layers of hardware and software. These tiers extend from the hardware deployed close to the machine, up to the software running on computers that operators use for control and monitoring. We are currently developing a new centrally supported service in the layers closest to the accelerator - Distributed I/O and Fieldbus. A key aspect of this project is the selection of industrial standards for the layers, which are currently dominated by custom, in-house designed solutions. Regarding the Distributed I/O layer, this paper describes how we are adapting CompactPCI Serial (CPCI-S) to be suitable as the low-cost modular hardware platform for remote analog and digital I/O applications in radiation-exposed as well as radiation-free areas. We are designing a low cost 3U chassis with a CPCI-S backplane accompanied by a radiation tolerant, switched-mode power supply and an FPGA-based System Board. Regarding the Fieldbus layer, the paper focuses on the radiation-tolerant implementation of the Industrial Ethernet protocol, Powerlink., Proceedings of the 17th International Conference on Accelerator and Large Experimental Physics Control Systems, ICALEPCS2019, New York, NY, USA

Background: Little information is available on ureteral or vesical involvement in Henoch-Schönlein syndrome. To determine the features of this condition we performed a formal analysis of peer-reviewed scientific literature on this topic. Methods: The US National Library of Medicine database was used as the data source. All articles published as full-length articles or letters were collected. Reports published in languages other than English, French, German, Italian or Spanish were not considered. Results: We analyzed 32 reports describing 35 cases (24 male and 11 female subjects aged between 3.5 and 63, median 7.0years) with ureteral (n = 30), vesical (n = 4), or both ureteral and vesical involvement (n = 1). The presentation included colicky abdominal pain, macroscopic hematuria (sometimes containing blood clots), urinary tract infection or urinary retention. The diagnosis of ureteral involvement was often fortuitous. Patients with vesical involvement were managed conservatively. However, the majority of those with ureteral involvement were managed surgically. Conclusions: Ureteral or vesical involvement is unusual and likely underappreciated in Henoch-Schönlein syndrome. Improved recognition and wider appreciation of this involvement can help to avoid associated morbidity. Management must be individualized for each patient. A multidisciplinary approach may be of value in planning medical treatment, surgical intervention, and follow-up.

The High Luminosity LHC project (HL-LHC) calls for the doubling of the beam intensity injected from the Super Proton Synchrotron (SPS). This is not possible with the present RF system consisting of four 200 MHz cavities. An upgrade was therefore launched, consisting of the installation of two more cavities during the machine shutdown in 2019-2020 (LS2). Installation of more cavities requires the installation of extra Low Level RF (LLRF) electronics. The present LLRF system consists of the original equipment installed in the 1970s, plus some additions dating from the late 1990s when the SPS was commissioned as LHC injector. The High-Power RF up-grade has motivated a complete renovation of the LLRF during LS2; use of a MicroTCA platform, use of a digital deterministic link for synchronization (the so-called White Rabbit), use of an absolute clock for the processing, new algorithms for reducing the cavity impedance, and a complete re-design of the beam control loops and slip-stacking., Proceedings of the 10th Int. Particle Accelerator Conf., IPAC2019, Melbourne, Australia