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We present a design of the scalable processor capable of providing an artificial neural network (ANN) functionality and in-house developed tools for automatic conversion of an ANN model designed with the TensorFlow library into an HDL code. The hardware is described in SystemVerilog and the synthesized module of the processor can perform calculations of a neural network with the speed exceeding 100 MHz. Our in-house designed software tool for ANN conversion supports translation of an arbitrary multilayer perceptron neural network into a state machine module, which performs necessary calculations. It is also dynamically reconfigurable so that the ANN operating on the hardware can be changed after it is deployed as an ASIC. The project aims the in-pixel implementation towards an X-ray photon energy estimation. The energy estimation shall be delivered with accuracy that exceeds the accuracy of an ADC converter that feeds the ANN with data.

A Rigaku XSPA-500k detector was evaluated and its performance characterized on the Metrology beamline at Synchrotron SOLEIL together by the SOLEIL Detector Group, AGH-UST and Rigaku., Hybrid photon counting (HPC) detectors are widely used at both synchrotron facilities and in-house laboratories. The features of HPC detectors, such as no readout noise, high dynamic range, high frame rate, excellent point spread function, no blurring etc. along with fast data acquisition, provide a high-performance detector with a low detection limit and high sensitivity. Several HPC detector systems have been developed around the world. A number of them are commercially available and used in academia and industry. One of the important features of an HPC detector is a fast readout speed. Most HPC detectors can easily achieve over 1000 frames s−1, one or two orders of magnitude faster than conventional CCD detectors. Nevertheless, advanced scientific challenges require ever faster detectors in order to study dynamical phenomena in matter. The XSPA-500k detector can achieve 56 kframes s−1 continuously, without dead-time between frames. Using ‘burst mode’, a special mode of the UFXC32k ASIC, the frame rate reaches 1 000 000 frames s−1. XSPA-500k was fully evaluated at the Metrology beamline at Synchrotron SOLEIL (France) and its readout speed was confirmed by tracking the synchrotron bunch time structure. The uniformity of response, modulation transfer function, linearity, energy resolution and other performance metrics were also verified either with fluorescence X-rays illuminating the full area of the detector or with the direct beam.

We report on the design of an active feedback circuit for charge sensitive amplifiers used for reading out hybrid pixel detectors. The predominant advantages of the proposed feedback over the existing solutions are its low noise, stability, and tunability. In addition, the circuit occupies small silicon area, which is crucial for hybrid pixel detectors. This paper presents both the mathematical analysis of the proposed circuit and measurement results obtained with the test structure.

Spectrally selective X-ray imaging provides improved material and tissue discrimination in comparison with the state-of-the-art dual energy technologies that are commonly used in medical, industrial, and security applications. Cadmium telluride (CdTe)- and cadmium zinc telluride (CdZnTe)-based line scanners and small size two-dimensional X-ray sensors are emerging to the market, but the need for large-scale panels is axiomatic. In this study, a seamless CdTe tile was developed that enables the implementation of large-sized, energy selective X-ray detector panels. The developed tile consists of a $64\times64$ pixel array (with $150~\mu \text{m}$ pitch) with a necessary substrate, ASIC, and CdTe crystal. The performance of the constructed seamless tile was characterized by focusing on spectral resolution and stability. In addition, a simple pixel trimming method that automates the equalization of each energy selective pixel was developed and analyzed. The obtained results suggest that the proposed concept of seamless (tileable) detector structures is a feasible approach to scale up panel sizes. The seamless tile shows comparable spectral resolution and stability performance with commercial CdTe sensors. The effect of tile to tile variation, the realization of a large-scale panel, as well as the charge sharing performance were left out of the scope and are to be studied in the next phase.

The advent of high-speed x-ray photon correlation spectroscopy now allows the study of critical phenomena in fluids to much smaller length scales and over a wider range of temperatures than is possible with dynamic light scattering. We present an x-ray photon correlation spectroscopy study of critical fluctuation dynamics in a complex fluid typical of those used in liquid-liquid extraction (LLE) of ions, dodecane-DMDBTDMA with extracted aqueous $\mathrm{Ce}({\mathrm{NO}}_{3}{)}_{3}$. We observe good agreement with both static and dynamic scaling without the need for significant noncritical background corrections. Critical exponents agree with 3D Ising values, and the fluctuation dynamics are described by simple exponential relaxation. The form of the dynamic master curve deviates somewhat from the Kawasaki result, with a more abrupt transition between the critical and noncritical asymptotic behavior. The concepts of critical phenomena thus provide a quantitative framework for understanding the structure and dynamics of LLE systems and a path forward to new LLE processes.

We present the CBM physics performance study for measurements of the higher order cumulants of the net-proton multiplicity distributions. These observables are proxy for net-baryon fluctuations and are commonly used to study the phase structure of QCD phase diagram. The simulation is done for $Au+Au$ collision at beam kinetic energy $E_{lab} = 10$ AGeV. The cumulants of net-proton distributions have been calculated at midrapidity ($|��y| =1$) for the transverse momentum range $0.2 < p_T < 2.0$ GeV/c. The centrality dependence of cumulants of net-proton upto order four is presented. The efficiency and detector effects are corrected using unfolding techniques. This work shows that the higher order cumulants of net-proton can be measured using the CBM detector., Proceedings of the XXVIII th International Conference on Ultrarelativistic Nucleus-Nucleus Collisions (Quark Matter 2019), Wuhan, China, November 3-9 2019

New physics experiments at the Facility for Antiproton and Ion Research (FAIR) in Darmstadt require application-optimized detector readout circuits. The STS/MUCH-XYTER2 (or SMX2) is a new, 128-channel prototype ASIC for silicon strip detectors and gas electron multiplier (GEM) detectors in the Compressed Baryonic Matter (CBM) experiment. It provides self-triggered amplitude and time measurement of incoming charge and serial streaming of digitized data. The 10 mm × 6.75 mm chip was fabricated employing the UMC CMOS 180 nm process. It comprises of an analog front-end with dual-path processing including a timing comparator in one path and a continuous-time 5-bit analog-to-digital converter in the other path, a digital back-end with time pre-sorting, advanced monitoring and throttling features and multiple 320 Mbps, serial links targeted for a GBT-based data acquisition structure. Specific conditions of the detector systems will be discussed prior to the structure and the features of the ASIC together with measurement results.

This paper presents the design of a PXF40—an ultrafast single photon-counting (SPC) readout front-end electronics implemented in a CMOS 40-nm technology dedicated to hybrid pixel detectors. The prototype application specific integrated circuit core is a matrix of 432 pixels ( $24\times 18$ ) with a $100\,\,\mu \text {m}\times 100\,\,\mu \text{m}$ size. The single processing channel consists of a charge-sensitive amplifier (CSA), a discriminator, and a 24-bit counter with logic circuitry. The input signal is amplified and formed only by the CSA stage. Depending on the CSA input transistor current value, it can operate in two modes: FAST and FAST_HC with higher current. The measured power dissipation per channel $P = 45 \,\,\mu \text{W}$ and noise $\text {ENC} = 212\,\, \text {e}^{-}$ rms for the FAST mode, while $P=100\,\,\mu \text{W}$ and ENC = 185 e− rms for the FAST_HC mode, respectively. The readout chip can count up to 1.2 Gcps/mm2 based on 10% dead-time loss input rate parameter, which is currently the fastest SPC-based solution.

X-ray imaging of moving objects using line detectors remains the most popular method of object content and structure examination with a typical resolution limited to 0.4–1 mm. Higher resolutions are difficult to obtain as, for the detector in the form of a single pixel row, the narrower the detector is, the lower the image Signal to Noise Ratio (SNR). This is because, for smaller pixel sizes, fewer photons hit the pixel in each time unit for a given radiation intensity. To overcome the trade-off between the SNR and spatial resolution, a two-dimensional sensor, namely a pixel matrix can be used. Imaging of moving objects with a pixel matrix requires time-domain integration (TDI). Straightforward TDI implementation is based on the proper accumulation of images acquired during consecutive phases of an object’s movement. Unfortunately, this method is much more demanding regarding data transfer and processing. Data from the whole pixel matrix instead of a single pixel row must be transferred out of the chip and then processed. The alternative approach is on-chip TDI implementation. It takes advantage of photons acquired by multiple rows (a higher SNR), but generates similar data amount as a single pixel row and does not require data processing out of the chip. In this paper, on-chip TDI is described and verified by using a single photon counting two-dimensional (a matrix of 128 × 192 pixels) CdTe hybrid X-ray detector with the 100 µm × 100 µm pixel size with up to four energy thresholds per pixel. Spatial resolution verification is combined with the Material Discrimination X-ray (MDX) imaging method.

This paper presents the detailed characterization of a single photon counting chip, named CHASE Jr., built in a CMOS 40-nm process, operating with synchrotron radiation. The chip utilizes an on-chip implementation of the C8P1 algorithm. The algorithm eliminates the charge sharing related uncertainties, namely, the dependence of the number of registered photons on the discriminator’s threshold, set for monochromatic irradiation, and errors in the assignment of an event to a certain pixel. The article presents a short description of the algorithm as well as the architecture of the CHASE Jr., chip. The analog and digital functionalities, allowing for proper operation of the C8P1 algorithm are described, namely, an offset correction for two discriminators independently, two-stage gain correction, and different operation modes of the digital blocks. The results of tests of the C8P1 operation are presented for the chip bump bonded to a silicon sensor and exposed to the 3.5- $\mu \text{m}$ -wide pencil beam of 8-keV photons of synchrotron radiation. It was studied how sensitive the algorithm performance is to the chip settings, as well as the uniformity of parameters of the analog front-end blocks. Presented results prove that the C8P1 algorithm enables counting all photons hitting the detector in between readout channels and retrieving the actual photon energy.

Nowadays, single photon counting pixel hybrid detectors are becoming increasingly popular in high-energy physics, X-ray detectors for synchrotron applications, and medical imaging. Readout chips for these detectors usually have the area of a few square centimeters and are designed to be abutted on three sides. However, many applications require large-area detectors without dead areas. The through-silicon vias (TSVs) aim to minimize the dead area and in that way to enable development of four-side buttable large-area detectors. AGH, Krakow, and IZM, Berlin, have undertaken a common effort to apply TSV (via last) technology to the readout integrated circuit called UFXC32k containing a matrix of $128 \times 256$ pixels, with a pixel pitch of $75~\mu \text{m}$ and a total area of 2 cm2. The TSVs were applied to the 87 I/O pads located at the bottom of UFXC32k IC. A TSV diameter of $20~\mu \text{m}$ was chosen while the wafers were thinned to $100~\mu \text{m}$ . The redistribution layer and the array of pads for solder bumping were distributed at the bottom side of the chips. Two UFXC32k chips with TSVs were attached to a single, 320- $\mu \text{m}$ -thick silicon sensor and finally, the chip detector modules were attached to low-temperature co-fired ceramic boards. The $2 \times 2$ cm2 plug-in detector modules were successfully built and tested.

A combined X-ray photon correlation spectroscopy and rheology study is carried out to capture the evolution of structure, fast particle-scale dynamics, and moduli (elastic and loss) at early times of gel formation near the fluid–gel boundary of a suspension of nanoparticles. The system is comprised of moderately concentrated suspensions of octadecyl silica in decalin (ϕ = 0.2) undergoing thermoreversible gelation. Near the gel boundary, the rate of gel formation is very sensitive to changes in attraction strength. However, we find that at different attraction strengths, the system goes through identical intermediate states of microscopic and macroscopic behavior, even though the absolute time needed to form a gel varies by orders of magnitude. We identify a single dimensionless time parameter, tw/tg, where tw is the wait time following the quench and tg is the rheologically determined gel time, that captures the similarity in gel formation at a range of attraction strengths. Following a temperature quench below the gel boundary, the system is initially fluidlike and forms diffusive clusters (∼8.5 times the particle diameter). After a lag-time, tL, clusters aggregate to form a network like structure which is characterized by the onset of mechanical rigidity and a rapid growth in microscopic relaxation times. At tg, the Baxter parameter obtained from adhesive hard sphere fits of the structure factor attains a constant value corresponding to the theoretical percolation boundary, thus demonstrating that gelation is percolation driven.

The Compressed Baryonic Matter (CBM) experiment at FAIR aims to study the area of the QCD phase diagram at high net baryon densities and moderate temperatures using heavy-ion collisions. The FAIR accelerator will provide high-intensity heavy-ion beams up to Au ions in the beam momentum range 3.5A-12A GeV/c per nucleon. In order to achieve it's physics goals and to perform multi-differential measurements of rare probes such as multistrange hadrons or hypernuclei, CBM plans to operate at unprecedented peak interaction rates of up to 10 MHz. Following an introduction into the physics program of the CBM, recent developments related to the preparation of the experiment, physics performance studies, and detector components tests within the so-called FAIR PHASE-0 program are discussed. In particular, the status of the mCBM project at GSI, which operated with high-intensity beams for the first time last year and combines various CBM detector subsystems with a common data acquisition system (DAQ), are presented.

The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

X-ray photon correlation spectroscopy is performed using a dual counter pixel array detector at a frame rate of 11.8 kHz with no readout dead-time., Small-angle scattering X-ray photon correlation spectroscopy (XPCS) studies were performed using a novel photon-counting pixel array detector with dual counters for each pixel. Each counter can be read out independently from the other to ensure there is no readout dead-time between the neighboring frames. A maximum frame rate of 11.8 kHz was achieved. Results on test samples show good agreement with simple diffusion. The potential of extending the time resolution of XPCS beyond the limit set by the detector frame rate using dual counters is also discussed.

This paper presents a readout integrated circuit called UFXC32k, designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The UFXC32k integrated circuit, designed in a CMOS 130 nm process, contains about 50 million transistors in the area of $9.64\;\hbox{mm} \times 20.15\;\hbox{mm}$ . The core of the IC is a matrix of $128 \times 256$ square-shaped pixels of ${\hbox{75}}\;\mu\hbox{m}$ pitch. Each pixel contains a charge sensitive amplifier, a shaper, two discriminators, and two 14-bit ripple counters. The analog front-end electronics allow processing of sensor signals of both polarities (holes and electrons). The UFXC32k chip is bump-bonded to a pixel silicon sensor and is fully characterized using X-ray radiation. The measured equivalent noise charge for the standard settings is equal to $123\ {{\rm e}^ - }\;\hbox{rms}$ (for the peaking time of 40 ns) and each pixel dissipates $26\;\mu\hbox{W}$ . Thanks to the use of trim blocks working in each pixel independently, an effective offset spread calculated to the input is only $9\ {{\rm e}^ - }\;\hbox{rms}$ with a gain spread of 2%. The maximum count rate per pixel depends mainly on effective CSA feedback resistance. Dead time in the front end can be set as low as 85 ns. In the continuous readout mode, a user can select the number of bits read out from each pixel to optimize the UFXC32k frame rate, e.g., for a readout of 2 bits/pixel with 200 MHz clock, the frame rate is equal to 23 kHz.

We report on a novel technique of an in-pixel multilevel offset correction to be used in hybrid pixel detector readout circuits operating in a single photon counting mode. This technique was implemented in a prototype integrated circuit consisting of 23,552 square shaped pixels of $75\ \mu \hbox{m}$ pitch, which was designed and manufactured in CMOS 130 nm technology. Each pixel contains a charge sensitive amplifier, shaper, two discriminators, two 14-bit counters and a block for multilevel offset correction. The effective gain and offset are controlled individually in each pixel. The measurement results prove very good uniformity of the prototype integrated circuit with an offset spread of only 7 ${{\rm e}^ - }{\rm rms}$ and a gain spread of 2.5%.

The vertically integrated photon imaging chip (VIPIC1) pixel detector is a stack consisting of a 500- $\mu \text{m}$ -thick silicon sensor, a two-tier 34- $\mu \text{m}$ -thick integrated circuit, and a host printed circuit board (PCB). The integrated circuit tiers were bonded using the direct bonding technology with copper, and each tier features 1- $\mu \text{m}$ -diameter through-silicon vias that were used for connections to the sensor on one side, and to the host PCB on the other side. The 80- $\mu \text{m}$ -pixel-pitch sensor was the direct bonding technology with nickel bonded to the integrated circuit. The stack was mounted on the board using Sn-Pb balls placed on a 320- $\mu \text{m}$ pitch, yielding an entirely wire-bond-less structure. The analog front-end features a pulse response peaking at below 250 ns, and the power consumption per pixel is 25 $\mu \text{W}$ . A successful completion of the 3-D integration is reported. In addition, all pixels in the matrix of $64\times 64$ pixels were responding on well-bonded devices. Correct operation of the sparsified readout, allowing a single 153-ns bunch timing resolution, was confirmed in the tests on a synchrotron beam of 10-keV X-rays. An equivalent noise charge of 36.2 $\text{e}^{-}$ rms and a conversion gain of 69.5 $\mu \text{V}/\text{e}^{-}$ with 2.6 $\text{e}^{-}$ rms and 2.7 $\mu \text{V}/\text{e}^{-}$ rms pixel-to-pixel variations, respectively, were measured.

We present the design and measurements of a proton detection system built using a single photon counting hybrid pixel array detector. The system uses the UFXC detector designed for operating with very high photon fluxes. We demonstrate, that with appropriately modified data acquisition firmware, the UFXC detector is capable of operating in the frame-triggered zero dead-time mode, which captures every frame containing desired information, at a rate of up to 50 kfps. The detector consists of a 128 x 256 matrix of square-shaped pixels with a pitch of 75 μ m , which makes it suitable for particle tracking applications in test beam environments. We estimate the position resolution achieved with a single layer of the UFXC detector to be around 40 μ m .

Hybrid pixel detectors are segmented devices used for particles detection, consisting of a sensor and readout electronics. To improve the resolution of the detector and allow operation with high-intensity photon fluxes, the pixel size is reduced. However, with decreasing pixel size, a charge sharing effect is more significant. To detect a photon irrespectively of charge sharing effect, the total photon energy should be reconstructed from fractional signals. Therefore, the algorithms dealing with charge sharing are developed [1–4]. The resolution of such detectors is limited by the pixel size, which must be large enough to fit all the functionality required by the complex algorithms. However, there are known methods that can improve the spatial resolution of a detector applied for high energy physics [5], or astronomy [6–8], and both photon counting detectors [9–11] and integrating detectors [12–14] are used. An alternative digital solution that can be implemented on-chip dedicated to hybrid pixel detectors working in a single photon counting mode is presented in this work. In this approach, charge sharing becomes the desired effect, since the information on the proportions of charge collected by the pixels can be used to estimate the photon interaction position with subpixel resolution. In the work analytical approach towards detector and readout channel modeling is used to state the requirements for the algorithm. The concept of the new digital on-chip algorithm is presented.