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This paper examines an embedded low-power techuique for the single-shot measurement of GHz digital signals. Two circuits will be demonstrated; the first is a rise time measurement core, while the second represents an embedded technique for the characterization of narrow pulses. Both circuits can be seen as general tools to increase the low-end time dynamic range measurements of digital events in CMOS. The circuits rely on a new fast voltage-crossing detector to convert the input information and condition it into same polarity edges, separated by the timing information to be measured. Those edges are then in turn stretched further using time amplification, making them easily detectable with low-resolution time-to-digital converters. Dynamic current generation techniques are used in the front-end detector to greatly reduce the power consumption. The proposed circuits are compact and introduce only a few tens of femtofarads capacitive loading. The circuits were implemented in a standard 0.18-[micro]m CMOS process. Experimental results show the feasibility of the proposed approach. Rise times of 1 ns and pulses as narrow as 78 ps were successfully captured in a single-shot measurement approach, with total power dissipation not exceeding a few milliwatts, in each of the two cases. Index Terms--CMOS, edge measurement, low power, mixed-signal testing, narrow pulse detection, on-chip measurement.

This paper examines the design and implementation of a fourth-order low-pass delta-sigma modulator using a systematic top-down design methodology. Special effort has been made to reduce the power consumption of the modulator through careful system-level modeling and synthesis of circuit specifications. Tradeoffs between circuit building block specifications, optimization time and computing resources are derived. This system-level modeling was tested through the successful implementation of a switched-capacitor delta-sigma analog-to-digital converter integrated circuit (IC) with an output rate slightly exceeding 2 MS/s, in a 1.8-V 0.18-[micro]m, single-polysilicon six-metal standard CMOS process. When sampled at 50 MHz, experimental results reveal that the IC achieves 77.6-dB dynamic range. The prototype consumes 18.8 mW of power, making it one of the lowest power dissipations in switched-capacitor implementations, and for applications where output rates exceed 2 MS/s. When compared to other state-of-the-art switched-capacitor modulators using a widely adopted figure of merit, the modulator dissipates less power and offers superior overall performance. Index Terms--Analog-to-digital converter (ADC), CMOS, delta-sigma ([DELTA][SIGMA]) modulation, low power, noise shaping, switched-capacitor circuits.

This paper will present a novel method to generate and distribute a synchronous clock to multiple nodes in a distributed system. Total system synchronization is established by adjusting the internal delays of each node so that the delay between all adjacent pairs of nodes becomes identical. The system is based on the principles of phase-locked and delay-locked loops but does not discuss the methods and details of phase acquisition, jitter or lock-in time. The system is composed of a master node used to generate clock pulses and multiple slave nodes used to align the pulses. A Matlab Monte Carlo simulation of the linear behavior of the system is presented which not only validates the theoretical description, but also can be used as a good tool to gauge the performance of any particular system scenario. Selected HSpice simulations are then presented which show the operating characteristics of certain scenarios involving differing interconnect lengths between nodes that correspond to specific Matlab simulations. Index Terms--Clock, distributed, phase-locked loop (PLL), synchronization.

A simple log-domain integrator that operates nominally with a supply voltage of 1.2 V is proposed. It does not employ p-n-p or positive metal-oxide-semiconductor (PMOS) transistors in the signal path. This has two advantages: 1) It makes the integrator suitable for high-frequency applications. 2) The circuit can be implemented using low-cost bipolar processes rather than the more expensive bipolar complementary metal-oxide-semiconductor (BiCMOS) processes or the bipolar processes featuring high-quality p-n-p transistors. A third-order Chebyshev prototype filter, employing the proposed integrator, is realized using a semicustom bipolar array. It consumes 282 [micro]A per pole for a cutoff frequency of 1.5 MHz, achieving a 40.5 dB dynamic range. For lower biasing currents, the circuit can operate from a supply voltage as low as 0.9 V. Detailed experimental results are reported and discussed. Index Terms--Analog integrated circuits, companding, continuous-time filters, current-mode circuits, integrator, log-domain filters, low power, low voltage, n-p-n only, nonlinear circuits, tunable filters.

This paper presents significant improvements in the generation of analog signals for on-chip analog circuit testing. In particular, the novel oscillators proposed here can achieve signal-to-noise ratios (SNR's) far greater than previous designs while remaining area efficient. One particular example illustrates a 30-dB improvement in the SNR. Alternatively, signals can be generated with the same SNR as with older designs but over a wider range of frequencies. Multitone and bandpass signal generation are enhanced in the same fashion. Stability was studied empirically. Prototypes were built and satisfactorily tested on field-programmable gate array technology. Index Terms - Oscillators, self-testing, sigma-delta modulation, signal processing, testing.

A transistor-level all n-p-n differential log-domain integrator geared toward low-distortion very high-frequency (VHF) applications is proposed. Systematic design steps are suggested and used to realize second and higher order balanced bandpass filters, based on the method of operational simulation of doubly-terminated LC ladders. We discuss the special sensitivity of log-domain integrators to small dc biasing offsets, practical issues in the design of the input and output interface stages, and the effect of parasitic resistors and capacitors on high-frequency log-domain filters. Experimental results from a 0.8-[[micro]meter] BiCMOS implementation of a single-ended 220-MHz biquad and a balanced 130-MHz fourth-order bandpass filter are reported, with emphasis on their distortion characteristics. Index Terms - Analog integrated circuits, companding, continuous-time filters, current-mode circuits, log-domain, nonlinear circuits, tunable filters, VHF filters.

This brief presents the design of an analog oscillator capable of generating multitone signals by encoding the information in an oversampled delta-sigma modulated one-bit stream. With the exception of low-pass filter, the proposed design is completely digital allowing accurate control of the amplitude, frequency, and phase of all sinusoids making up the multitone signal. Simulations and FPGA experiments performed to date have verified the performance of the proposed design. Index Terms - Self-testing, sigma-delta modulation, signal generators, testing.

A technique for the design of log-domain filters is introduced which is based on the operational simulation of LC ladders. The method is used to design a fifth-order Chebyshev and elliptic filter. HSPICE simulation results and experimental results are shown with emphasis on frequency behavior and linearity. The filters showed good correlation between the original filter specifications and the measured frequency response. They proved to be easily tunable and could be operated up to 1 MHz or one tenth of the [f.sub.T] of the slowest transistor. Total harmonic distortion and intermodulation distortion was measured with results up to -47 and -55 dB, respectively.

This paper describes a high-quality analog oscillator for low-frequency applications, which uses a combination of over-sampling and delta-sigma modulation. With the exception of a lowpass filter and a 1-bit D/A, the proposed circuit is entirely digital, providing accurate control over the oscillation frequency and amplitude. At the core of the oscillator is a digital simulation of an LC-tank circuit consisting of two cascaded integrators. This arrangement guarantees oscillation by constraining the poles of the resonator to locations on the z-plane unit-circle, even in a finite-precision implementation. To minimize circuit complexity, the entire oscillator is operated at the oversampled rate, thereby eliminating the associated interpolation filter. Furthermore, the incorporation of a delta-sigma modulator inside the resonator loop leads to a very efficient implementation requiring only 4 multi-bit adders and a 2-input multiplexor. The desired analog signal may be recovered by lowpass filtering the 1-bit output of the delta-sigma modulator. Experiments performed thus far have indicated an effective dynamic range exceeding 80 dB.

The switched-current (SI) technique has recently been proposed as a cheaper alternative to the switched-capacitor (SC) technique. This stems largely from the fact that the analog signal processing functions performed by a SC circuit using linear capacitors and MOS transistors can be replaced by a SI circuit consisting solely of MOS transistors. At this time, most of the SI circuit design techniques and analysis have dealt strictly with the linear behavior of SI circuits. But, since SI circuits use only MOS transistors to perform linear processing, it seems apparent to ask the question: How linear are SI circuits? In this paper we shall identify a major source of distortion in SI memory circuits and derive an explicit formula that bounds the Total Harmonic Distortion (THD) that results from this source of distortion. Also, the frequency range over which this type of distortion dominates will be discussed. Both simulation and experimental results verify the proposed theory.