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Your search keyword '"Rodrigues, Joachim"' showing total 132 results
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132 results on '"Rodrigues, Joachim"'

1. Improving practical sensitivity of energy optimized wake-up receivers: proof of concept in 65nm CMOS

Author

Mazloum, Nafiseh Seyed, Rodrigues, Joachim Neves, Andersson, Oskar, Nejdel, Anders, and Edfors, Ove

Subjects
Computer Science - Information Theory
Abstract

We present a high performance low-power digital base-band architecture, specially designed for an energy optimized duty-cycled wake-up receiver scheme. Based on a careful wake-up beacon design, a structured wake-up beacon detection technique leads to an architecture that compensates for the implementation loss of a low-power wake-up receiver front-end at low energy and area costs. Design parameters are selected by energy optimization and the architecture is easily scalable to support various network sizes. Fabricated in 65nm CMOS, the digital base-band consumes 0.9uW (V_DD=0.37V) in sub-threshold operation at 250kbps, with appropriate 97% wake-up beacon detection and 0.04% false alarm probabilities. The circuit is fully functional at a minimum V_DD of 0.23V at f_max=5kHz and 0.018uW power consumption. Based on these results we show that our digital base-band can be used as a companion to compensate for front-end implementation losses resulting from the limited wake-up receiver power budget at a negligible cost. This implies an improvement of the practical sensitivity of the wake-up receiver, compared to what is traditionally reported., Comment: Submitted to IEEE Sensors Journal

Published
2016
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6. Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-V t Domain By Architectural Folding

Author

Rodrigues, Joachim Neves, Akgun, Omer Can, Acharya, Puneet, de la Calle, Adolfo, Leblebici, Yusuf, Öwall, Viktor, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Monteiro, José, editor, and van Leuken, René, editor

Published
2010
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12. Digital implementation of a wavelet-based event detector for cardiac pacemakers

Author

Rodrigues, Joachim Neves, Olsson, Thomas, Sornmo, Leif, and Owall, Viktor

Subjects
Pacemaker, Artificial (Heart) -- Research, Wavelet analysis, Business, Computers and office automation industries, Electronics, Electronics and electrical industries
Abstract

This paper presents a digital hardware implementation of a novel wavelet-based event detector suitable for the next generation of cardiac pacemakers. Significant power savings are achieved by introducing a second operation mode that shuts down 2/3 of the hardware for long time periods when the pacemaker patient is not exposed to noise, while not degrading performance. Due to a 0.13-[micro]m CMOS technology and the low clock frequency of 1 kHz, leakage power becomes the dominating power source. By introducing sleep transistors in the power-supply rails, leakage power of the hardware being shut off is reduced by 97%. Power estimation on RTL-level shows that the overall power consumption is reduced by 67% with a dual operation mode. Under these conditions, the detector is expected to operate in the sub-[micro]W region. Detection performance is evaluated by means of databases containing electrograms to which five types of exogenic and endogenic interferences are added. The results show that reliable detection is obtained at moderate and low signal to noise-ratios (SNRs). Average detection performance in terms of detected events and false alarms for 25-dB SNR is [P.sub.D] = 0.98 and [P.sub.FA] = 0.014, respectively. Index Terms--Cardiac pacemaker, event detector, gated supply, sleep transistors, wavelet filter.

Published
2005

16. A Wide-Operating Range Standard-Cell Based Memory in 28nm FD-SOI

Author

Andersson, Oskar, Mohammadi, Babak, and Rodrigues, Joachim Neves

Subjects
ddc:621.3
Abstract

This study presents an energy-efficient ultra-low voltage standard-cell based memory in 28nm FD-SOI. The storage element (standard-cell latch) is replaced with a full- custom designed latch with 50 % less area. Error-free operation is demonstrated down to 450mV @ 9MHz. By utilizing body bias (BB) @ VDD = 0.5 V performance spans from 20 MHz @ BB=0V to 110MHz @ BB=1V.

Published
2016

26. 65‐nm CMOS low‐energy RNS modular multiplier for elliptic‐curve cryptography.

Author

Asif, Shahzad, Andersson, Oskar, Rodrigues, Joachim, and Kong, Yinan

Abstract

Modular multiplication (MM) is the main operation in cryptography algorithms such as elliptic‐curve cryptography (ECC) and Rivest–Shamir–Adleman, where repeated MM is used to perform elliptic curve point multiplication and modular exponentiation, respectively. The algorithm for the proposed architecture is derived from the Chinese remainder theorem and performs MM completely within a residue number system (RNS). Moreover, a 40‐channel RNS moduli‐set is proposed for this architecture to benefit from the short‐channel width of the RNS moduli‐set. The throughput of the architecture is enhanced by pipelining and pre‐computations. The proposed architecture is fabricated as an ASIC using 65‐nm CMOS technology. The measurement results are obtained for energy dissipation at different voltage levels from 0.43 to 1.25 V. The maximum throughput of the proposed design is 1037 Mbps while operating at a frequency of 162 MHz with an energy dissipation of 48 nJ. The proposed architecture enables the construction of low‐voltage and energy‐efficient ECCs. [ABSTRACT FROM AUTHOR]

Published
2018
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28. När blir man 'självständig' forskare vid LTH?

Author

Hulteberg, Christian, Isaksson, Hanna, Sohl, Christian, Rodrigues, Joachim, and Rusek, Fredrik

Subjects
Electrical Engineering, Electronic Engineering, Information Engineering
Published
2012

32. A

Author

Rodrigues, Joachim, Akgun, OmerCan, and Öwall, Viktor

Subjects
Hardware_INTEGRATEDCIRCUITS, Electrical Engineering, Electronic Engineering, Information Engineering
Abstract

This paper presents the hardware implementation of a wavelet based event detector for cardiac pacemakers. A high level energy estimation flow was applied to evaluate energy efficiency of standard-cell based designs, over several CMOS technology generations, from 180 to 65 nm, operated in the sub-threshold domain. The simulation results indicate a 65 nm low-leakage high-threshold (LL-HVT) CMOS technology as the favourable choice. Accordingly, the design was fabricated in 65 nm LL-HVT CMOS. Measurements validate the simulation results and prove that the circuit is fully functional down to a supply voltage of 250mV. At the energy minimum voltage of 320mV the circuit dissipates 0.88 pJ per sample at a clock rate of 20 kHz.

Published
2010

33. A <1 pJ sub-VT Cardiac Event Detector in 65 nm LL-HVT CMOS

Author

Rodrigues, Joachim, Akgun, OmerCan, and Öwall, Viktor

Subjects
Hardware_INTEGRATEDCIRCUITS, Electrical Engineering, Electronic Engineering, Information Engineering
Abstract

This paper presents the hardware implementation of a wavelet based event detector for cardiac pacemakers. A high level energy estimation flow was applied to evaluate energy efficiency of standard-cell based designs, over several CMOS technology generations, from 180 to 65 nm, operated in the sub-threshold domain. The simulation results indicate a 65 nm low-leakage high-threshold (LL-HVT) CMOS technology as the favourable choice. Accordingly, the design was fabricated in 65 nm LL-HVT CMOS. Measurements validate the simulation results and prove that the circuit is fully functional down to a supply voltage of 250mV. At the energy minimum voltage of 320mV the circuit dissipates 0.88 pJ per sample at a clock rate of 20 kHz.

Published
2010

35. A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility

Author

Kamuf, Matthias, Öwall, Viktor, Rodrigues, Joachim, and Anderson, John B

Subjects
CMOS, Electrical Engineering, Electronic Engineering, Information Engineering, flexible chips, integrated circuits, Viterbi decoder
Abstract

This paper discusses design and measurements of a flexible Viterbi decoder fabricated in 130-nm digital CMOS. Flexibility was incorporated by providing various code rates and modulation schemes to adjust to varying channel conditions. Based on previous trade-off studies, flexible building blocks were carefully designed to cause as little area penalty as possible. The chip runs down to a minimal core supply of 0.8V. It turns out that striving for more modulation schemes is beneficial in terms of power consumption once the price is paid for accepting different code rates viz. radices in the trellis and survivor path units.

Published
2008

41. Ultra low power transceivers for wireless sensors and body area networks

Author

Sjoland, Henrik, primary, Anderson, John B., additional, Bryant, Carl, additional, Chandra, Rohit, additional, Edfors, Ove, additional, Johansson, Anders J, additional, Mazloum, Nafiseh Seyed, additional, Meraji, Reza, additional, Nilsson, Peter, additional, Radjen, Dejan, additional, Rodrigues, Joachim, additional, Sherazi, Yasser, additional, and Owall, Viktor, additional

Published
2014
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