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This work presents a novel approach to a Hardware Root-of-Trust that leverages System-on-Chip technology for the implementation of hardware cryptographic functions. Taking advantage of the processing power of a System-on-Chip, the solution established promotes hardware-based security solutions over software-only solutions. The proposed Root-of-Trust, developed around a Xilinx Zynq-7000 SoC device, integrates components based on cryptographic algorithms and physical phenomena. This innovative Root-of-Trust is tailored to support a spectrum of security tasks within cryptographic systems, including device-specific identifiers and keys, encryption and decryption, hashing, and signature generation and verification. The study adopts a unified design methodology, capitalizing on collaborative efforts to efficiently develop hardware primitives that significantly contribute to enhancing security in computing environments. Aligned with the advantages of reconfigurable hardware, this Hardware Root-of-Trust addresses the critical need for robust hardware-level security and introduces a set of countermeasures to fortify the design against potential threats.

This work presents the design and validation of a compact and efficient RO-PUF/TRNG module, which combines ID generation and entropy source functionalities, and can be used as an essential primitive of a hardware RoT for RISC-V based SoCs. The design was encapsulated as an IP core to provide it with a high level of configurability, flexibility, and reusability. A comprehensive SDK for online characterization, validation, and performance monitoring of PUF and TRNG quality metrics was also developed. The experimental results show that the proposed RO-PUF/TRNG IP is suitable for increasing the security of IoT applications.

In the age of digital systems ubiquity, designing specialized solutions requires tailored tools. Proprietary software and hardware may present limitations that hinder future adaptability, thus, open-source design tools have emerged as an alternative solution to overcome these issues. They offer benefits such as being free, flexible, customizable, and community-driven. This paper evaluates and compares the design flow of a symmetric cipher implemented on Xilinx Zynq 7000 SoC devices using Xilinx Vivado software against Lattice iCE40 LP/HX devices using APIO open-source software tools. The comparison has been made in terms of performance, functionality, and cost. The methodology involved evaluating design requirements, features, support options, and testing to provide an analysis of the advantages and disadvantages of each tool highlighting the trade-offs between open-source and proprietary design tools.

The proliferation of devices for the Internet of Things (IoT) and their implication in many activities of our lives have led to a considerable increase in concern about the security of these devices, posing a double challenge for designers and developers of products. On the one hand, the design of new security primitives, suitable for resource-limited devices, can facilitate the inclusion of mechanisms and protocols to ensure the integrity and privacy of the data exchanged over the Internet. On the other hand, the development of techniques and tools to evaluate the quality of the proposed solutions as a step prior to their deployment, as well as to monitor their behavior once in operation against possible changes in operating conditions arising naturally or as a consequence of a stress situation forced by an attacker. To address these challenges, this paper first describes the design of a security primitive that plays an important role as a component of a hardware-based root of trust, as it can act as a source of entropy for True Random Number Generation (TRNG) or as a Physical Unclonable Function (PUF) to facilitate the generation of identifiers linked to the device on which it is implemented. The work also illustrates different software components that allow carrying out a self-assessment strategy to characterize and validate the performance of this primitive in its dual functionality, as well as to monitor possible changes in security levels that may occur during operation as a result of device aging and variations in power supply or operating temperature. The designed PUF/TRNG is provided as a configurable IP module, which takes advantage of the internal architecture of the Xilinx Series-7 and Zynq-7000 programmable devices and incorporates an AXI4-based standard interface to facilitate its interaction with soft- and hard-core processing systems. Several test systems that contain different instances of the IP have been implemented and subjected to an exhaustive

This paper presents the validation of a novel approach for a true-random number generator (TRNG) based on a ring oscillator–physical unclonable function (RO-PUF) for FPGA devices. The proposal takes advantage of the different noise sources that affect the electronic implementation of the RO-PUF to extract the entropy required to guarantee its function as a TRNG, without anything more than minimal changes to the original design. The new RO-PUF/TRNG architecture has been incorporated within a hybrid HW/SW embedded system designed for devices from the Xilinx Zynq-7000 family. The degree of randomness of the generated bit streams was assessed using the NIST 800-22 statistical test suite, while the validation of the RO-PUF proposal as an entropy source was carried out by fulfilling the NIST 800-90b recommendation. The features of the hybrid system were exploited to carry out the evaluation and validation processes proposed by the NIST publications, online and on the same platform. To establish the optimal configuration to generate bit streams with the appropriate entropy level, a statistical study of the degree of randomness was performed for multiple TRNG approaches derived from the different implementation modes and configuration options available on the original RO-PUF design. The results show that the RO-PUF/TRNG design is suitable for secure cryptographic applications, doubling its functionality without compromising the resource–efficiency trade-off already achieved in the design.

Programmable devices combine powerful processing systems with a rich infrastructure of general-purpose and specific logic blocks, making it possible the efficient implementation of embedded systems to perform complex tasks by facilitating hardware acceleration of critical stages to improve their performance. Based on these characteristics, a hardware implementation of a genetic algorithm for circle detection in digital images is described in this paper. The detection system has been designed for Xilinx Zynq-7000 and Zynq UltraScale+ family devices and implemented on two low-cost development boards that reach acceleration factors of 33.12 and 37.3, respectively, when compared to the fully software implementation. Detection results from both development boards have been compared using synthetic and real images from different scenarios. The accuracy and performance achieved demonstrate the suitability of this proposal to design embedded systems with restricted size, resources and energy consumption for applications in Internet of Things, Industry 4.0 and other related paradigms.

In recent years, the strategy of co-designing Hardware/Software (HW/SW) systems has been widely adopted to exploit the synergy between both approaches thanks to technological advances that have led to more powerful devices providing an increasingly better cost–benefit trade-off. This paper presents an HW/SW system for the detection of multiple circles in digital images based on a genetic algorithm. It is implemented on an Ultra96-v2 development board, which contains a Xilinx Zynq UltraScale+ MPSoC device and supports a Linux operating system that facilitates application development. The design is powered by developing an interactive computing environment by means of the Jupyter Notebook platform, in which different programming languages coexist. The specific advantages of each of these languages have been used to describe the hardware component that accelerates the evolutionary computation for circle detection (VHDL), to execute SW-HW interaction functions, as well as the pre- and post-processing of the images (ANSI-C) and to code, evaluate, and document the system execution process (Python). As a result, a computationally efficient application was obtained, with high accuracy in the detection of circles in synthetic and real images, and with a high degree of reconfigurability that provides the user with the necessary tools to incorporate it in a specific area of interest.

The generation of unique identifiers extracted from the physical characteristics of the underlying hardware ensures the protection of electronic devices against counterfeiting and provides security to the data they store and process. This work describes the design of an efficient Physical Unclonable Function (PUF) based on the differences in the frequency of Ring Oscillators (ROs) with identical layout due to variations in the technological processes involved in the manufacture of the integrated circuit. The logic resources available in the Xilinx Series-7 programmable devices are exploited in the design to make it more compact and achieve an optimal bit-per-area rate. On the other hand, the design parameters can also be adjusted to provide a high bit-per-time rate for a particular target device. The PUF has been encapsulated as a configurable Intellectual Property (IP) module, providing it with an AXI4-Lite interface to ease its incorporation into embedded systems in combination with soft- or hard-core implementations of general-purpose processors. The capability of the proposed RO-PUF to generate implementation-dependent identifiers has been extensively tested, using a series of metrics to evaluate its reliability and robustness for different configuration options. Finally, in order to demonstrate its utility to improve system security, the identifiers provided by RO-PUFs implemented on different devices have been used in a Helper Data Algorithm (HDA) to obfuscate and retrieve a secret key.

The implementation of true random number generators is of vital importance to preserve the reliability of cryptographic systems. The lack of entropy can compromise their integrity, affecting the security of the entire chain of applications. Ensuring the effectiveness of a random number generator can be understood as reducing the risk of information loss due to possible attacks by third parties. This paper presents a novel approach for a true random number generator based on a Ring Oscillator-Physical Unclonable Function. Since the principle of operation of physical unclonable functions is based on the physical properties of each device, they can be used for security applications such as device identification, counterfeit prevention, and increase the robustness of cryptographic functions. In addition, increasing the versatility of the design to use them as a source of entropy, they can also fulfill tasks such as generation of initialization vectors or nonces and keys for symmetric cryptography. The system incorporates multiple operating configurations, which allows a complete analysis of its performance to adapt it to different application scenarios. The randomness and correct operation of the proposed design have been evaluated online, by incorporating it into a hybrid HW/SW embedded system able to run the official test suite published by the National Institute of Standards and Technology without any need for post-processing. The architecture has been designed for Xilinx Zynq-700 family devices and implemented on the Pynq-Z2 development board.