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11 results on '"Rolandi, Pierluigi"'

1. An On-Chip Flip-Flop Characterization Circuit

Author

Jain, Abhishek, Veggetti, Andrea, Crippa, Dennis, Rolandi, Pierluigi, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, van Leuken, René, editor, and Sicard, Gilles, editor

Published
2011
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2. Novel Methodology for Assessing Chip-Package Interaction Effects onChip Performance

Author

Kteyan, Armen, primary, Choy, Jun-Ho, additional, Sukharev, Valeriy, additional, Bertoletti, Massimo, additional, Maiorca, Carmelo, additional, Zadra, Rossana, additional, Inzaghi, Massimo, additional, Gattere, Gabriele, additional, Zinco, Giancarlo, additional, Valente, Paolo, additional, Bardelli, Roberto, additional, Valerio, Alessandro, additional, Rolandi, Pierluigi, additional, Monetti, Mattia, additional, Cuomo, Valentina, additional, and Santapà, Salvatore, additional

Published
2022
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10. Panel.

Author

Casale-Rossi, Marco, Rolandi, Pierluigi, Bruening, Andreas, Domic, Antun, Kress, Rainer, Sawicki, Joseph, Sebeke, Christian, and Bosch, Robert

Published
2012

11. Panel: What is EDA doing for trailing edge technologies?

Author

Casale-Rossi, Marco, Rolandi, Pierluigi, Bruening, Andreas, Domic, Antun, Kress, Rainer, Sawicki, Joseph, and Sebeke, Christian

Abstract

Over the last decade, the semiconductor industry has advanced CMOS technology from 90 to 22/20 nanometers, and the EDA industry has developed a great deal of tools, methodologies, and flows to help “gigascale” design, implementation and verification, at these “leading edge” technology nodes. However, in 2010 approximately 75% of design starts used 130 nanometers or greater CMOS technologies [1], and 25% of wafers were fabricated using these “trailing edge” technologies [2]. There are possibly more designers working at 130 nanometers and above than at 90 nanometers and below, and there is certainly much more to electronics than just digital CMOS and microprocessors, and in order for the electronic industry to continue delivering on promises, “More than Moore” is needed, besides “More of Moore”. What is EDA doing - or what should EDA do - in order to help design implementation and verification at trailing edge technologies? [ABSTRACT FROM PUBLISHER]

Published
2012
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