Search

Experiments in nuclear physics, biomedicine and astronomy often require pulse-counting electronics for large numbers of channels. This paper describes an event-counting system attached to 60 channels of an innovative monolithic array of Single-Photon Avalanche Diodes (SPADA) intended for astronomical use. The system can capture events with pulse-counting rates of up to 20 MHz, a minimum integration time of 10 [micro]s, which results in a data acquisition rate of 100 000 frames per second. It can also store several hours' worth of data. This performance is achieved in a system that offers a high degree of flexibility, is small in size and has a low cost. The implementation is based on a Commercial-Off-The-Shelf (COTS) single board, fitted with an FPGA and a DSP. This board is connected to a PC by means of an IEEE 1394 high-speed serial link which stores the collected data and functions as a TCP/IP server. The data acquisition parameters, as well as the collected data, can be accessed by means of a custom-designed interface running on a TCP/IP client. A proof-of-concept system has been assembled and some test stand results are presented and discussed. Index Terms--Astronomy, counting circuits, digital signal processors, field programmable gate arrays, imaging, radiation detectors.

A theoretical analysis of the effects of the delay-line differential nonlinearity (DNL) on the typical performance parameters of high-resolution time-to-digital converters (TDCs) based on delay-locked-loop (DLL) delay lines has been developed. The theoretical study is based on the knowledge of the delay-line nonlinearity values that can be measured, with the desired precision, by means of a statistical code-density test. In particular, the effects on the TDC time resolution and error standard deviation curve as a function of the measured time interval are investigated. An a posteriori linearization technique, consisting in a proper correction of the TDC readouts, is then analyzed and its advantages are theoretically demonstrated. Finally, the theoretical results are superimposed on experimental data coming from a real TDC. The measured deviations from the ideal behavior are thus justified and can just be ascribed to the delay-line nonlinearity. Index Terms--Delay-locked-loop (DLL) delay lines, differential nonlinearity (DNL), high-resolution time measurement, linearization technique, time-to-digital converter (TDC).

This paper presents a CMOS realization of a time-to-digital converter (TDC) for nuclear physics experiments. An innovative and robust architecture, already used in a previous TDC version with 1 ns of bin size, has been adopted and improved with the aim to achieve a 500-ps bin size. The TDC has eight input channels plus a common channel. It can store up to 32 events per channel with a double-hit resolution of 8 ns. It can realize common-start and common-stop operations. It has 4.2 ms of input range with a 125-MHz system clock. The chip uses an asynchronous interpolator system based on a delay-locked line to increase the coarse resolution. It has been fabricated in a double-metal single poly n-well, 1-[[micro]meter] CMOS process with an area of about 77 [mm.sup.2]. Measurements show that the TDC has better performance compared to similar devices, especially the time resolution below 250 ps. Index Terms - Application specific integrated circuit, delay lines, delay lock loop, time measurements.