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This article reports GaN super-heterojunction Schottky barrier diodes (SHJ-SBDs) with substantially improved performance. Metal-2DEG sidewall n-ohmic contacts were deployed to achieve low contact resistance of $0.75~\Omega ~ \cdot ~mm$ , avoiding the risk of abnormally high contact resistance caused by inaccurate etch depth control. A pGaN notch formed near the cathode successfully eliminated excessive hole conduction caused by the sidewall n-ohmic contact. Isolation was improved by a high-energy Al implantation step. The resulting SHJ-SBD exhibited a breakdown voltage (BV) of ~12.5 kV and a specific resistance of 100.8 $\text{m}\Omega ~ \cdot ~cm^{2}$ .

Varistors are technologically important for their large energy handling capabilities and highly nonlinear electrical behavior when voltages above a characteristic switch field are applied. It is generally accepted that the prototypical ZnO–Bi2O3 varistor system forms electrostatic Schottky barriers at grain boundaries in response to residual Bi and other dopants left at grain surfaces during Bi2O3 segregation. While barrier heights can be modulated with formulation and defect chemistry, mechanisms by which dopant locations, defect compensation, and local phases determine varistor behavior are not completely understood. Bulk studies are challenging due to random grain boundary formation and difficulties studying individual boundaries. To circumvent these challenges in the ZnO–Bi2O3 varistor system, we use as-deposited and post-heat-treated thin film ZnO–Bi2O3 prototypes to simulate bulk varistor grain boundary phase formation and investigate resulting defect chemistry. Characterizing interactions between Bi2O3 films deposited on thin film and single-crystal ZnO by XRD and TEM-EDS revealed primarily Zn-out diffusion, resulting in two (Bi2O3)1−x(ZnO)x, or BZO, phases. Using these results, we present a saturated front model correlating changes in Bi2O3 thickness to phase evolution. We subsequently explore the influence of MnO doping leading to substantial changes in phase evolution for post-heat-treated (Mn:ZnO)–Bi2O3 stacks. Dopant-controlled Bi2O3 phase formations yield a 12 × difference, on average, between nonlinear coefficients for γ*- and β*-BZO.

GaN based electronic devices have gained great success in the arena of high-frequency and high-power applications. A high-quality GaN MOS structure has the potential to enable new device designs and higher device performance, thereby bringing the success of GaN electronics to a new level. This paper discusses results of the work on GaN MOS structures show that with adequate surface preparation samples featuring interface trap density down to the ~ 1010 eV-1cm-2 range can be formed.

This letter reports an experimental demonstration of charge-balanced GaN super-heterojunction Schottky barrier diodes (SHJ-SBDs). Charge balance between the n-type delta-doping and the p-type doping was achieved by adjusting the thickness of the pGaN. This device structure enabled scaling of breakdown voltage to over 3 kV, and dynamic switching up to 2.8 kV without using any field-plate.

We present a systematic study on the design of a novel GaN/AlGaN/GaN super-heterojunction Schottky diode. Through physics-based TCAD simulation, we discuss three important design aspects: 1) how to design a GaN/AlGaN/GaN structure to form a high-density 2-D electron gas and to scale it to multiple vertically stacked channels with less risk in reaching the critical thickness limited by the strain in epitaxy; 2) how to reach charge balance and how sensitive is the breakdown voltage with respect to the doping imbalance; and 3) how to ensure that the processes of depleting and accumulating electrons and holes in the structure are fast enough for practical power switching applications.

Varactors, with its capacitance tunable by the applied voltage, are enabling components for reconfigurable RF systems. The performance of a varactor could be characterized by its ${Q}$ -factor and the capacitance tuning ratio. In this article, we seek to develop a new varactor with very high ${Q}$ -factor and large tuning ratio, enabling reconfigurable RF systems with large bandwidth. There were two main innovations in varactor diode design. One was the use of the fin structure, in which the electrodes were placed on two opposite sidewalls of the mesa structure instead of one on top and the other at the bottom or next to the mesa. This design eliminates the extrinsic series resistance in the conventional varactor diode designs, leading to substantially increased ${Q}$ -factor. The other was the use of a multichannel structure. The structure was composed of multiple AlGaN/GaN heterojunctions with high-mobility 2-D electron gas. The high-mobility electron gas helped lowering the intrinsic series resistance, thereby further improving the ${Q}$ -factor.

In this paper, we present GaN super-heterojunction Schottky barrier diodes (SHJ-SBDs) with over 10 kV blocking voltage. Charge imbalance between the n-type delta doping and the p-type doping was adjusted by N+ implantation. This device structure enabled scaling of breakdown voltage to over 10 kV and with an on-resistance of $1054 \Omega \cdot\text{mm}$ .

To achieve the first demonstration of non-polar a-plane gallium nitride (GaN) epitaxy on (0 1 0) gallium oxide substrates by metal organic chemical vapor deposition (MOCVD), a low temperature AlGaN nucleation layer was engineered. Specific low temperature AlGaN growth parameters were necessary because the gallium oxide substrate begins to decompose at ∼600 °C in the ambient of H2. To achieve a smooth GaN epitaxial surface, low V/III molar ratio, and low pressure were required. To characterize the GaN film, AFM along with an orientation-dependent crystal tilt mosaic study by X-ray diffraction was performed. We effectively reduced threading dislocation density by applying in situ SiN interlayers grown by MOCVD. The oxygen contamination in the GaN film was found to originate from the substrate decomposition during GaN growth and can be reduced more than 10 times by using GaN buffer layer grown under N2 ambient.

The extremely high concentration of the electric field near the drain corner of the gate is the major cause for premature breakdown and local hotspot formation of AlGaN/GaN high electron mobility transistors (HEMTs). This hotspot negatively impacts the device performance, reliability, lifetime, and limits the operability envelope. Metal field plates have been used to mitigate this electric field concentration. However, it has been proven difficult to reach the theoretical breakdown voltage of GaN using conventional field plate structures. In this work, a novel “resistive field plate” structure based on amorphous indium-gallium-zinc-oxide (a-IGZO) was constructed to minimize the electric field concentration by imposing a linear voltage boundary condition on the device surface, between the drain and source electrodes. Standard electrical testing and state-of-the-art optical thermography techniques were used to understand the electro-thermal interactions behind the improvement in electrical and thermal performance of AlGaN/GaN metal-oxide-semiconductor HEMTs (MOS-HEMTs) employing the a-IGZO resistive field plate. The novel field plated design resulted in ∼25% increase in the device breakdown voltage (V B ) and ∼24% reduction in the channel peak temperature as compared to a control sample employing no field plate structures. Key knowledge obtained from this study provides insight into enhancing the performance and reliability of AlGaN/GaN HEMTs and also suggests a viable solution that may enable the full exploitation of the potential of wide bandgap and ultra-wide bandgap lateral power electronic devices.

GaN metal–oxide–semiconductor structures were fabricated by atomic layer deposition of aluminum oxynitride thin films on bulk GaN substrates with c-, a-, and m-plane surfaces. Capacitance–voltage measurements ranging from 5 kHz to 1 MHz were conducted at room temperature. The interface trap number density (Nit) and interface trap level density (Dit) of the devices were extracted. A Nit of less than 2 × 1011 cm−2 and a Dit of less than 2 × 1011 cm−2 eV−1 were obtained on the a-plane and m-plane samples. Nit and Dit values were larger for c-plane samples, with the largest interface trap density observed on the c-plane sample with the highest dislocation density. The different Nit and Dit values can be attributed to different dislocation densities and dangling bond densities among different samples.

This letter reports a GaN vertical trench metal–oxide–semiconductor field-effect transistor (MOSFET) with normally-off operation. Selective area regrowth of n+-GaN source layer was performed to avoid plasma etch damage to the p-GaN body contact region. A metal-organic-chemical-vapor-deposition (MOCVD) grown AlN/SiN dielectric stack was employed as the gate “oxide”. This unique process yielded a 0.5-mm2-active-area transistor with threshold voltage of 4.8 V, blocking voltage of 600 V at gate bias of 0 V, and on-resistance of $1.7~\Omega $ at gate bias of 10 V.

The rise of cryogenic technologies such as quantum computing [P. Platzman and M. Dykman, Science 284, 1967 (1999)] calls for semiconductor devices that can operate efficiently and with low thermal leak at low temperatures. To better understand the behavior of light-emitting diodes (LEDs) at these extreme temperatures, we derive the LED forward characteristics in the case of an InGaAs single-quantum well. We demonstrate the benefits of composition grading for increasing LED current, especially at low temperatures. This is done by deriving the optimum indium composition as a function of position. The results of the derivation are compared with COMSOL Multiphysics simulations and are found to match well.

The Power MOSFET Tool through Synopsys® Saber® can estimate static and dynamic behaviors of devices given measured static and dynamic characteristic curves. Model parameters are made accessible for behavior simulation and design optimization even if a datasheet is unavailable or more advanced device properties are in developmental stages. This functionality makes the tool ideal for predicting the behavior of a new GaN semiconductor in a circuit. Therefore, this paper first demonstrates a SiC model with accurate static and dynamic waveforms confirming the efficacy of the tool beyond Si. Second, this paper presents a model of a vertical GaN transistor using the Power MOSFET Tool which is compared against experimental static and dynamic measurements. The vertical GaN subcircuit model matches the experimental static results within 8.42% error. The model predicts the 8.48 ns turn-on and 30.2 turn-off time within a couple nanoseconds. With optimization of the parasitic elements in the circuit, the model matches the rise and fall rates as well as the frequency and magnitude of the ringing. Therefore, the model would simulate reliable switching times and losses critical for predicting devices’ behavior in prospective applications.

In this chapter, we discuss III-nitride lateral transistors for power switching applications. GaN-based transistors have the capabilities of delivering high current, handling high voltage, and switching at high speed. These are exactly what are needed for the next-generation power electronics with better efficiency, smaller form factor and lower cost. Development of GaN power switching transistor largely leveraged the work done for making GaN microwave transistors. In order for the GaN transistors to be used for power switching, several modifications to the GaN microwave transistor technology needs to be made. One is the normally-off operation. Power electronics circuits require the switches to be normally-off for safe circuit startup. A second one is the high-voltage operation. While most of today's microwave transistors operate between 28 and 48 V, power switching transistors often operate at 400–480 V. A third one is the use of Si substrates. While GaN-on-SiC structures are most common for microwave transistors, GaN-on-Si structures are needed for power switching transistors for lower cost and better manufacturability. In Section 1 , we discuss technologies to enable normally-off operation. In Section 2 , we discuss high-voltage operation of GaN transistors. In Section 3 , we discuss impact of using Si substrates on power switching characteristics. In Section 4 , we discuss factors limiting the performance of GaN-on-Si lateral transistor power switching performance.

This work presents a procedure for creating high-fidelity TCAD models of lateral GaN/AlGaN FETs. This modeling process is based on iterative refinement using experimental data as well as known device geometry. By tuning charge density in the channel of the device and scattering under the gate, both the transfer and forward curves of the device were accurately modeled. Knowledge of device geometry and anisotropic physics was used to accurately model the non-linear terminal capacitances of the device. This modeling procedure was performed on both a recessed gate device with full knowledge of the device's geometry. The model developed here will be used in future work to assess the impact of design decisions.

Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here.

Vertical GaN power semiconductors promise higher power with faster switching speeds but the development of this technology has been slowed. This is due to the expense and lack of familiarity with GaN substrates. This paper will detail the functionality of HRL's cutting-edge vertical GaN transistor which is mounted onto a specially made PCB and tested. The testing consists of a static characterization which shows a breakdown voltage of 600 V, as well as the transfer characteristics, output characteristics, and the on-state resistance with respect to current. The device is then switched at various voltages and currents with voltage switching speeds up to 97 V/ns. The device is successfully switched up to 450 V under a 2 A load current.

As a wide bandgap semiconductor with high breakdown field, GaN is expected to outperform the incumbent Si technology for power switching applications. Advances in GaN epitaxial growth, device technology, and circuit implementations have resulted in high-performing power switches based on the GaN high electron mobility transistor (HEMT) structure. Demonstrated system benefits have validated the real value of GaN power switching technology. However, the full potential of GaN power switching technology is still far from being exploited. Various factors, including the size of electrodes and wiring, non-optimal E-field shaping, and substrate capacitive coupling, are limiting the performance of GaN HEMT power switches. Emerging device structures, such as, vertical transistors and multichannel superjunction transistors, have the potential to overcome some of those limitations, thereby bringing the performance benefits of the GaN power switching technology to a new level. Understanding the underlying physics is important to the success of the emerging device structures.

This letter reports the first demonstration of gallium nitride (GaN) complementary metal–oxide–semi-conductor (CMOS) field-effect-transistor technology. Selective area epitaxy was employed to have both GaN N-channel MOSFET (NMOS) and P-channel MOSFET (PMOS) structures on the same wafer. An AlN/SiN dielectric stack grown by metal–organic chemical vapor deposition served as the gate oxide for both NMOS and PMOS, yielding enhancement-mode N- and P-channel with the electron mobility of 300 cm2/V-s and hole mobility of 20 cm2/V-s, respectively. Using the GaN CMOS technology, a functional inverter integrated circuit was fabricated and characterized.

Short-gate AlGaN/GaN heterostructure field-effect transistors (HFETs) with extremely thin AlGaN barrier layers were fabricated and characterized from the viewpoint of millimeter-wave applications. The devices showed good direct current and small-signal characteristics; however, the 30-GHz power characteristics were degraded due to frequency dispersion caused by the SiNx/AlGaN interface states. The dispersive behavior of the thin barrier devices measured in pulse I-V curves was different from the commonly observed one for the devices with normal AlGaN barrier thicknesses of 20-30 nm. The first characteristic point was that it happened only for structures with extremely thin barrier layers. As another unique point, the drain current collapse in the pulsed modes was observed only at a positive gate bias. We consider that the unique dispersion of the thin barrier HFETs was caused by the different charging paths related to hot electrons accelerated in a high electric field region of a 2-D electron gas (2DEG) channel. It seems reasonable to suppose that, for the extremely thin barrier structures, the AlGaN surface states can be charged not only by injected electrons from the gate metal through the SiNx/AlGaN interface but also by the hot electrons overcoming the barrier from the 2DEG formed at the AlGaN/GaN interface.

Field effect transistors (FETs) on both GaN and AlGaN buffers were grown and compared. Development of high quality AlGaN is the key to obtain high performance AlGaN buffer FETs. An optimized Al0.04Ga0.96N layer on SiC substrate had (002) and (201) X-ray rocking curves with full wide at half maximum (FWHM) of 140 and 450 arc sec, respectively, indicates the comparable crystal quality of AlGaN to that of a typical GaN layer. X-ray reciprocal space mapping and ω –2θ scans showed that the AlGaN barriers grown on GaN and Al0.04Ga0.96N buffers had different Al compositions and thickness, which was attributed to the compositional pulling effect. At room temperature, the AlGaN buffer FET had a sheet carrier concentration and electron mobility of 8.3×1012 cm-2 and 1750 cm2/Vs, respectively. AlGaN/GaN/AlGaN FETs demonstrated a status-of-the-art power added efficiency (PAE) of 53.5%, and a status-of-the-art power gain of 13.4 dB at a drain bias of 20 V at 30 GHz. This device also exhibited lower output conductance and better pinch-off due to the improved electron confinement resulting from the increase in the effective buffer energy height. The device results imply that AlGaN buffer FETs are promising devices for highly scaled transistors in RF applications in the Ka- band and beyond. (© 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

We present a high-performance SiN/AlGaN (cap)/GaN (channel)/AlN (barrier)/GaN (buffer) metal-insulator-semiconductor high-electron-mobility transistor grown on the N-face, in which the 2-D electron gas (2DEG) is induced at the top GaN/AlN interface. The use of AlN eliminates alloy disorder scattering to the 2DEG and provides strong back-barrier confinement of the 2DEG under high electric fields for device scaling. Devices with 0.7-mum gate length showed a current-gain cutoff frequency (fT) of 17 GHz and a power-gain cutoff frequency (f max) of 37 GHz. A continuous-wave output power density of 7.1 W/mm was measured at 4 GHz, with 58% power-added efficiency and a large-signal gain of 15.3 dB at a drain bias of 35 V.

N-face AlGaN (cap)/GaN (channel)/AlGaN (barrier)/GaN (buffer) high electron mobility transistors (HEMTs) provide a simple solution for strong confinement of the two-dimensional electron gas (2DEG) from the back since carriers are induced on top of the AlGaN barrier. To reduce the adverse effects of random alloy scattering from the AlGaN barrier, an N-face GaN-spacer HEMT was designed with an epi-structure consisting of an AlGaN (cap)/GaN (channel)/AlN/GaN (spacer)/AlGaN (barrier)/GaN (buffer). The 2DEG is confined at the GaN (channel)/AlN interface, while the GaN-spacer layer separates the 2DEG from the AlGaN barrier. The large polarization-induced electric field of the AlN and its large conduction band discontinuity with GaN provide strong confinement for good pinch-off and low output conductance under high electric fields. Up to 20% improvement in electron mobility was measured in these devices. The devices showed a current gain cut-off frequency (f t ) of 24 GHz and power gain cut-off frequency (f max ) of 44 GHz for a nominal gate length of 0.7 μm. An output power density of 4.5 W/mm was measured at 4 GHz, with 34% power added efficiency and a gain of 10.3 dB at a drain bias of 40 V.

GaN-on-Si switches, hard-switching 400V at 1MHz, have demonstrated power conversion with 96% efficiency, outperforming Si MOSFETs. This performance was achieved using hybrid integration of bare GaN and gate driver die, resulting in clean waveforms with a slew rate of 100V/ns. The new Si Super-Junction (SJ) MOSFETs have a hard-switching figure-of-merit (FOM) which is approaching that of GaN HFETs. However, GaN's FOM for soft-switching is more than 9X better than Si SJMOSFET. Using this FOM, GaN ICs in 400V soft-switching converters are predicted to switch beyond 100MHz.

We evaluate the AlxGa1–xN/GaN/AlyGa1–yN double heterostructure (DH) for heterostructure field-effect transistor applications, where the GaN quantum well is compressively strained on a relaxed crack-free AlyGa1–yN buffer layer, so that the Al content in the AlxGa1–xN top barrier can be improved as compared with a conventional AlxGa1–xN/GaN single heterostructure (SH) with the same strain in the AlxGa1–xN layer. By self-consistently solving the coupled Schrodinger and Poisson equations, we find that the two-dimensional electron gas (2DEG) sheet density in an Al0.6Ga0.4N/GaN/Al0.3Ga0.7N DH is 2.59 × 1013 cm–2, much higher than the 1.71 × 1013 cm–2 in a conventional Al0.3Ga0.7N/GaN SH. The 2DEG sheet density increases with increasing Al content x and decreases slightly with increasing y . With a fixed Al content (x – y ) ratio, y is the key parameter determining the 2DEG density. (© 2006 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Gate-drain current-voltage characteristics in unpassivated AlGaN/GaN high electron mobility transistors (HEMTs) grown by metal-organic chemical vapor deposition (MOCVD) on sapphire substrates were investigated. Under a fixed V/III ratio for AlGaN layer growth, the growth window for getting low gate leakage and good two-dimensional electron gas mobility is narrow. We designed a multi-step growth of the AlGaN for HEMTs, i.e., high-V/III-ratio AlGaN layer starting from the AlGaN/GaN interface, then low-V/III-ratio AlGaN layer, which yielded the best 2DEG mobility and also reduced gate leakage. It was also found that the forward current and reverse current before pinch off can be explained by the thin surface barrier (TSB) model, and the AlGaN layer grown under lower effective V/III ratio shows a larger surface donor density but smaller leaky area. (© 2005 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

We present the design, fabrication, and characterization of AlGaN-GaN double-channel HEMTs. Two carrier channels are formed in an AlGaN-GaN-AlGaN-GaN multilayer structure grown on a sapphire substrate. Polarization field in the lower AlGaN layer fosters formation of a second carrier channel at the lower AlGaN-GaN interface, without creating any parasitic conduction path in the AlGaN barrier layer. Unambiguous double-channel behaviors are observed at both dc and RF. Bias dependent RF small-signal characterization and parameter extraction were performed. Gain compression at a high current level was attributed to electron velocity degradation induced by interface scattering. Dynamic IV measurement was carried out to analyze large-signal behaviors of the double-channel high-electron mobility transistors. It was found that current collapse mainly occurs in the channel closer to device surface, while the lower channel suffers minimal current collapse, suggesting that trapping/detrapping of surface states is mainly responsible for current collapse. This argument is supported by RF large-signal measurement results.

The correlation between the resistivity of an undoped GaN/Al2O3 interfacial layer and in-situ reflectance spectrum in metalorganic chemical vapor deposition and the mechanism of this correlation were investigated. The first minimum reflectance during the initial high-temperature GaN growth was found to be a good indicator of the resistivity of the GaN buffer. The background electron concentration and mobility were both higher in the samples with higher indicative reflectance at that point. The resistivity of the GaN buffer layer was predominantly determined by an ∼0.25-µm-thick layer near the GaN/Al2O3 interface. Atomic force microscope (AFM) and high-resolution x-ray diffraction (HRXRD) results showed that the samples with higher indicative reflectance had smaller sized but higher density nuclei before the high-temperature GaN growth and lower screw threading dislocation (TD) density in the initially grown GaN. The difference in the background electron concentration and mobility of the interfacial layer was related to the relatively higher concentration of the O and Al diffused from Al2O3, which is also dependent on the size and density of the nuclei. These differences were found not to affect the structural and electrical properties or the surface morphology of AlGaN/GaN high electron-mobility transistors (HEMTs, except for the buffer conduction) when the GaN buffer is thick enough (e.g., ∼2.5 µm).

We report a novel GaN heterojunction field-effect transistor device that incorporates vertically scaled epilayers, a nanoscale gate with integrated staircase-shaped field plates, and regrown ohmic contacts. This device technology has an unprecedented combination of high breakdown (176 V), low ON-resistance (1.2 Ωmm), enhancement-mode operation (VTH=+0.35 V), and excellent high-frequency performance (fT/fmax=50/120 GHz), which enables new applications as a high-frequency power switch or a microwave power amplifier. The gate design manages the electric field at the drain edge of the gate, which mitigates dynamic ON-resistance degradation.

We present a systematic study on the admittance characterization of trap states in AlGaN/GaN heterostructures. An equivalent circuit model was developed to analyze the spatial location, energy distribution density, and time constant of the AlGaN/GaN trap states. Results show that AlGaN/GaN interface trap states are responsible for the trapping behavior in the 10 kHz–1 MHz frequency range. An increase of AlGaN layer thickness or Al composition leads to greater trap state density at the AlGaN/GaN interface. (© 2003 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

In this paper, we took a brief investigation on the properties of two-dimensional electron gas (2DEG) in AlGaN/InGaN/GaN heterostructures. Band profiles and the 2DEG distribution were calculated by self-consistently solving the Schrodinger and Poisson equations. Our calculated results indicate that the 2DEG concentration can be considerably increased with the incorporation of an InGaN layer. Quantum confinement, and thereby the 2DEG distribution are very sensitive to the strain of the incorporated InGaN layer. Hence one can design the 2DEG by incorporating proper InGaN layer into the conventional AlGaN/GaN heterostructures. These novel features are attributed to the strong polarization effect in AlGaN/InGaN/GaN heterostructures.

In this paper, Al/AlN/Si(1 1 1) metal–insulator–semiconductor (MIS) structure has been fabricated and their interfacial properties have been investigated using capacitance–voltage techniques. The dielectric constant of AlN was found to vary from 5.01 to 8.67 with the frequency decreasing from 1 MHz to 50 Hz due to the existance of a transition zone between AlN and Si substrate which is not forbidden to the electronics. The distribution of the interface states in the interface was extracted from the frequency-dependent capacitance–voltage characteristics of the MIS structure. The interface state density Dit in the silicon forbidden band gap was in the order of 1012 eV−1 cm−2 and the time constant was about 10−5 s through analyzing the capacitance as a function of frequency.

This letter reports high-voltage GaN field-effect transistors fabricated on Si substrates. A halide-based plasma treatment was performed to enable normally off operation. Atomic layer deposition of Al2O3 gate insulator was adopted to reduce the gate leakage current. Incorporation of multiple field plates, with one field plate connected to the gate electrode and two field plates connected to the source electrode successfully enabled a high breakdown voltage of 1200 V and low dynamic on-resistance at high-voltage operation.

High Electron Mobility Transistors (HEMTs) based on GaN are attractive for high-speed and high-voltage applications. The performance advantages of the GaN HEMTs rely on the high breakdown field of the GaN material and the high electron mobility of the 2-dimesional electron gas (2DEG) in the AlGaN/GaN heterojunction [1, 2]. In order to take full advantage of the excellent material properties, the shape of the electric-field distribution in the GaN HEMTs must be carefully optimized to operate the device at its highest switching speed while handling a large voltage swing. Without proper field-shaping, a high electric-field can cause electron injection into traps, hence degrading the output current and on-resistance during switching operation. This phenomenon is often referred to as dynamic on-resistance (Ron dynamic) degradation, current collapse or DC-RF dispersion. As an effective approach of shaping the electric-field, the use of field-plates in GaN HEMTs has received extensive studies [3]. For microwave applications, a V-shaped gate with integrated sloped field-plate was used to control the electric-field with minimal added capacitance associated with the field-plate [5, 6]. For high-voltage applications, a multiple field-plates structure was used to scale up the operating voltage [2, 4]. In this paper, we report a sloped field-plate approach for high-voltage applications.

This paper reports on trap-related shifts of the transfer curve and threshold voltage of power AlGaN/GaN HEMTs under switched bias operating life and reverse and forward DC bias stress. Opposite polarity threshold voltage shifts at room temperature under operating life and reverse bias stress conditions can be explained by means of drain current transient measurements under reverse bias stress conditions. A proposed model to explain the trapping/de-trapping behavior under different stress conditions is described and highlights the critical role of the electric field. Experimental evidence of the importance of the role of the electric field is seen in reduced parametric shift by improving the field plate design.

We report the performance of AlGaN buffer GaN high-electron mobility transistors (HEMTs) grown by metal-organic chemical vapor deposition. GaN HEMTs on high-quality AlGaN buffer were grown on SiC substrates. The incorporation of an AlGaN buffer into the GaN HEMT significantly improves channel confinement and suppresses the short-channel effect. Advanced deep-recess V-gate structures were employed to optimize the device for better microwave power performance. With a 10- nm GaN channel layer sandwiched between the AlGaN barrier and buffer, excellent power performance was achieved. The output power density is 13.1 W/mm, and the associated power-added efficiency is 72% at 4-GHz frequency and 48- V drain bias. This power performance is comparable to the state-of-the-art GaN HEMTs grown on GaN buffers, indicating that the AlGaN buffer in our optimized device structure does not introduce any noticeable trapping.

AlGaN/GaN high-electron-mobility transistors (HEMTs) with indium tin oxide (ITO) transparent gate electrodes have been fabricated. The transparent gate electrodes enable the investigation of photon, electron, and phonon behaviors in active regions in HEMTs using optical characterizations such as electroluminescence, photoluminescence, and Raman spectroscopy technologies. Leakage current, on/off ratio, and transparency have been compared for transistors using Ni/Au/Ni, ITO, and Ni/ITO stacks as gate electrodes. Compared to the Ni/Au/Ni gate transistor, the ITO gate device shows a comparable current gain cutoff frequency (f T) but a much lower power gain cutoff frequency (f max) due to the low conductivity of ITO.