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openaire: EC/H2020/704947/EU//ADVANTAG5 We present a prototype RF transmitter with an integrated multilevel class-D power amplifier (PA), implemented in 28-nm CMOS. The transmitter utilizes tri-phasing modulation, which combines three constant-envelope phase-modulated signals with coarse amplitude modulation in the PA. This new architecture achieves the back-off efficiency of multilevel outphasing, without linearity-degrading discontinuities in the RF output waveform. Because all signal processing is performed in the time domain up to the PA, the entire system is implemented with digital circuits and structures, thus also enabling the use of synthesis and place-and-route CAD tools for the RF front end. The effectiveness of the digital tri-phasing concept is supported by extensive measurement results. Improved wideband performance is validated through the transmission of orthogonal frequency-division multiplexing (OFDM) bandwidths up to 100 MHz. Enhanced reconfigurability is demonstrated with non-contiguous carrier aggregation and digital carrier generation between 1.5 and 1.9 GHz without a frequency synthesizer. For a 20-MHz 256-QAM OFDM signal at 3.5% error vector magnitude (EVM), the transmitter achieves 22.6-dBm output power and 14.6% PA efficiency. Thanks to the high linearity enabled by tri-phasing, no digital predistortion is needed for the PA.

The crowded radio spectrum allocated for 3G/4G mobile communication, together with the growing demand for higher data-rates, has led to the situation where transceivers need to support FDD operation in multiple frequency bands with different TX-RX duplex spacing. In order to reduce costs and enable SAW-less operation, many recent transmitter implementations have thus targeted stringent out-of-band (OOB) emission levels. Analog-intensive TX architectures achieve low OOB noise at the price of large area consumption, as complex reconstruction filters are used to suppress DAC quantization noise and image replicas [1,2]. On the other hand, due to the lack of analog filtering, digital-intensive TX architectures need 12-14b DAC resolution for low OOB noise, which complicates DAC design and typically requires DPD or calibration [3-5]. This work presents an RF transmitter implementing a fully digital solution to the aforementioned challenge. Instead of using bulky analog filtering or high resolution DAC, the disclosedTX employs digital ΔΣ modulation and mismatch shaping to attenuate the DAC noise at a programmable duplex distance. This solution enables -160dBc/Hz noise in the RX-band, by using only a 10b DAC without DPD, calibration or analog filtering.

Advanced wireless radio standards set stringent requirements on the bandwidth, frequency range and reconfigurability of base-station transmitters. Recently, the outphasing concept has shown promise of wide bandwidth while taking advantage of process scaling with extensive exploitation of rail-to-rail signaling. Recent outphasing transmitter designs have often focused on power-amplifier (PA) and power-combiner implementations while omitting the phase modulator [1,2]. Moreover, previously reported transmitters with integrated digital phase modulators have only shown bandwidths up to 40MHz [3,4], although 133MHz has been demonstrated at 10GHz carrier frequency utilizing phase modulators based on conventional IQ-DACs [5]. Thus, digital-intensive outphasing transmitters capable of modulation with hundreds of MHz bandwidth at existing cellular frequency bands have not yet been published. To address the aforementioned challenge, this paper introduces a multilevel outphasing transmitter with four amplitude levels, including the first prototype implementation based on the digital interpolating phase modulator concept [6]. The transmitter is targeted for 5G picocell base stations and has been verified to operate with instantaneous bandwidth up to 400MHz. In addition, the developed phase modulator eliminates the need for complex on-chip frequency synthesizers by introducing digital carrier frequency generation, demonstrated between 0.35 and 2.6GHz, while utilizing a single 1.8GHz reference clock.