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Your search keyword '"Ruhm, Matthias"' showing total 24 results
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24 results on '"Ruhm, Matthias"'

1. Advanced CD uniformity correction using radial basis function (RBF) models

Author

Groeger, Philip, primary, Denker, Ulrich, additional, Zech, Robin, additional, Buhl, Stefan, additional, Ruhm, Matthias, additional, Kim, Mingyu, additional, Jang, Hongseok, additional, Kang, Chunsoo, additional, Lee, DongYoung, additional, Kim, Hyunjun, additional, Park, Sukwon, additional, Kim, Bohye, additional, Lee, Honggoo, additional, Lee, Sangho, additional, Park, Chanha, additional, Choi, DongSub, additional, and Lee, Jeonghoon, additional

Published
2022
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5. Combined process window monitoring for critical features

Author

Hartig, Carsten, additional, Schulz, Bernd, additional, Melzer, Robert, additional, Ruhm, Matthias, additional, Fischer, Daniel, additional, Buhl, Stefan, additional, Habets, Boris, additional, Rößiger, Martin, additional, and Gutsch, Manuela, additional

Published
2017
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7. Scanner correction capabilities aware CMP lithography hotspot analysis

Author

Yang Qing, Perez Valerio, Narayana Samy Aravind, Sky Yeo, Ushasree Katakamsetty, Quek Shyue Fong, Hui Colin, Schiwon Roberto, and Ruhm Matthias

Subjects
Scanner, Optics, Resist, business.industry, Computer science, Hotspot (geology), business, Lithography, Line width, Design for manufacturability
Abstract

CMP effects on manufacturability are becoming more prominent as we move towards advanced process nodes, 28nm and below. It is well known that dishing and erosion occur during CMP process, and they strongly depend on pattern density, line spacing and line width [1] . Excessive thickness or topography variations can lead to shrinkage of process windows, causing potential yield problems such as resist lifting or printability issues. When critical patterns fall into regions with extreme topography variations, they would be more sensitive to defects and could potentially become yield limiters or killers. Scanner tools compensate and correct topography variations by following the given profile [2] . However the scanner exposure window size is wider compared to local topography variations in design. This difference would generate new lithography focus sensitive weak points which may be missed. Experiments have been conducted as shown in Fig 1. Design under manufacturing has been subjected to scanner tool topography focus corrections. Despite of the corrections, Site B topography height has worsened while site A and C shown some improvements. As a result, additional improvements need to be done to meet manufacturability requirements.

Published
2014
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8. Influence of the process-induced asymmetry on the accuracy of overlay measurements

Author

Shapoval, Tetyana, additional, Schulz, Bernd, additional, Itzkovich, Tal, additional, Durran, Sean, additional, Haupt, Ronny, additional, Cangiano, Agostino, additional, Bringoltz, Barak, additional, Ruhm, Matthias, additional, Cotte, Eric, additional, Seltmann, Rolf, additional, Hertzsch, Tino, additional, Hajaj, Eitan, additional, Hartig, Carsten, additional, Efraty, Boris, additional, and Fischer, Daniel, additional

Published
2015
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15. Use of scatterometry for scanner matching

Author

Bald, Holger, primary, Seltmann, Rolf, additional, Bubke, Karsten, additional, Ruhm, Matthias, additional, Noot, Marc, additional, Woischke, Dieter, additional, van Adrichem, Paul, additional, and Luehrmann, Paul, additional

Published
2011
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16. Improving lithographic performance for 32 nm

Author

Busch, Jens, primary, Parge, Anne, additional, Seltmann, Rolf, additional, Scholtz, Heike, additional, Schultz, Bernd, additional, Knappe, Uwe, additional, Ruhm, Matthias, additional, Noot, Marc, additional, Woischke, Dieter, additional, and Luehrmann, Paul, additional

Published
2010
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23. Characterizing interlayer edge placement with SEM contours.

Author

Weisbuch, François, Schatz, Jirka, and Ruhm, Matthias

Subjects
SCANNING electron microscopy, INTEGRATED circuits, EDGES (Geometry), SPECTRAL element method
Abstract

Background: The continuous scaling of integrated circuit requires not only a very good control of the device critical dimensions but also a very accurate control of the device overlay between layers to achieve satisfactory yields. These two critical factors can be combined to a single metric called interlayer edge placement error (EPEinterlayer) that quantifies the process margin necessary to keep a safe separation, extension, or overlap between the edges of a pattern in one layer with respect to another pattern in a second layer. Aim: The purpose of this work is to characterize with scanning electron microscopy (SEM), the EPEinterlayer and overlay variances of complex contact shapes relative to a poly layer to assess the contributions of the systematic and random EPEinterlayer. Approach: SEM images of a few etched patterns were recorded sequentially for both contact and poly features at the same locations on the wafer. Then, SEM contours were extracted, aligned, and overlapped to derive EPEinterlayer. One experiment was focusing on intrawafer EPEinterlayer characterization whereas another was studying more specifically intrafield overlay variations. For the latter experiment, systematic overlay errors were added to facilitate the comparison of the SEM-based method with respect to a reference image-based overlay (IBO) method. Results: The earliest direct metrology of EPEinterlayer and overlay in device enabled by this work shows a very high variability of EPEinterlayer and overlay errors across wafer and across field. Conclusions: By directly measuring the EPEinterlayer on devices that are not accessible by the standard method (optical IBO on OL structures), we showed the feasibility of this metrology and observed more dimensional variance in devices than recognized with IBO, thereby enabling better control of device pattern variation. [ABSTRACT FROM AUTHOR]

Published
2019
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