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Nowadays, the different computer tools available enable designers to create complex industrial prototypes. The use of these tools is constrained by the limitations imposed by common devices, such as screens and displays. Recently emerged virtual and augmented reality techniques have started being used as supports in many learning and industrial environments. Beyond the new possibilities that these tools offer for designing industrial objects, the underlying question is whether these new technologies could improve the creativity of designers to enable them to get a better understanding of the designing process itself. This paper presents a methodological proposal for the deployment of an industrial design engineering course aimed not only at learning different design techniques, but also at assessing the creativity skills of students. The practical contents include the use of virtual reality devices, to help the designer overcome the limitations of prototype visualisation and make better designing decisions. Moreover, a creativity test will be performed at the beginning and at the end of the course to assess the changes in creativity skills taking place within the experiment group versus the changes in a traditional learning (control) group. [ABSTRACT FROM PUBLISHER]

Local binary patterns (LBP) are an effective texture descriptor for face recognition. In this work, a LBPbased hybrid system for face recognition is proposed. Thus, the dimensionality of LBP histograms is reduced by using principal component analysis and the classification is performed with support vector machines. The experiments were completed using the challenging Indian Movie Face Database and show that our method achieves high recognition rates while reducing 95% the dimensions of the original LBP histograms. Moreover, our algorithm is compared against some state-of-the-art approaches. The results indicate that our method outperforms other approaches, with accurate face recognition results. [ABSTRACT FROM AUTHOR]

The sine cosine algorithm's main idea is the sine and cosine-based vacillation outwards or towards the best solution. The first main contribution of this paper proposes an enhanced version of the SCA algorithm called as ESCA algorithm. The supremacy of the proposed algorithm over a set of state-of-the-art algorithms in terms of solution accuracy and convergence speed will be demonstrated by experimental tests. When these algorithms are transferred to the business sector, they must meet time requirements dependent on the industrial process. If these temporal requirements are not met, an efficient solution is to speed them up by designing parallel algorithms. The second major contribution of this work is the design of several parallel algorithms for efficiently exploiting current multicore processor architectures. First, one-level synchronous and asynchronous parallel ESCA algorithms are designed. They have two favors; retain the proposed algorithm's behavior and provide excellent parallel performance by combining coarse-grained parallelism with fine-grained parallelism. Moreover, the parallel scalability of the proposed algorithms is further improved by employing a two-level parallel strategy. Indeed, the experimental results suggest that the one-level parallel ESCA algorithms reduce the computing time, on average, by 87.4% and 90.8%, respectively, using 12 physical processing cores. The two-level parallel algorithms provide extra reductions of the computing time by 91.4%, 93.1%, and 94.5% with 16, 20, and 24 processing cores, including physical and logical cores. Comparison analysis is carried out on 30 unconstrained benchmark functions and three challenging engineering design problems. The experimental outcomes show that the proposed ESCA algorithm behaves outstandingly well in terms of exploration and exploitation behaviors, local optima avoidance, and convergence speed toward the optimum. The overall performance of the proposed algorithm is statistically validated using three non-parametric statistical tests, namely Friedman, Friedman aligned, and Quade tests. [ABSTRACT FROM AUTHOR]

Abstract: In this paper we present a new technique for partial product reduction in multiplication operations. The method is based on the construction of counter elements by means of look-up tables. The organization of these counters into reduction trees takes advantage of the inherent benefits of the integration of the memories and provides an alternative to classic operation methods. We show several reduction schemes that illustrate the proposed technique and describe hybrid examples that combine stored logic with classic combinational counters in order to adapt them better to each scheme. Our approach outperforms other schemes used for comparison. In this sense, not only an independent technology model has been established, but also an FPGA approximation has been implemented to measure such factors in a real-life technology platform. [Copyright &y& Elsevier]

Several population-based metaheuristic optimization algorithms have been proposed in the last decades, none of which are able either to outperform all existing algorithms or to solve all optimization problems according to the No Free Lunch (NFL) theorem. Many of these algorithms behave effectively, under a correct setting of the control parameter(s), when solving different engineering problems. The optimization behavior of these algorithms is boosted by applying various strategies, which include the hybridization technique and the use of chaotic maps instead of the pseudo-random number generators (PRNGs). The hybrid algorithms are suitable for a large number of engineering applications in which they behave more effectively than the thoroughbred optimization algorithms. However, they increase the difficulty of correctly setting control parameters, and sometimes they are designed to solve particular problems. This paper presents three hybridizations dubbed HYBPOP, HYBSUBPOP, and HYBIND of up to seven algorithms free of control parameters. Each hybrid proposal uses a different strategy to switch the algorithm charged with generating each new individual. These algorithms are Jaya, sine cosine algorithm (SCA), Rao's algorithms, teaching-learning-based optimization (TLBO), and chaotic Jaya. The experimental results show that the proposed algorithms perform better than the original algorithms, which implies the optimal use of these algorithms according to the problem to be solved. One more advantage of the hybrid algorithms is that no prior process of control parameter tuning is needed. [ABSTRACT FROM AUTHOR]

Abstract: Emerging VLSI and ULSI integration technologies provide new possibilities for developing computational paradigms based on memories with pre-calculated data. A memory can behave like a processor with complete functionality by simulating a classic Turing machine. By means of this stored logic based architecture, the processor adopts a simple and regular internal organization. In addition, it makes the most of the inherent features in the memories and offers the possibility of reconfiguration by writing new results inside of it. This paper reviews different possibilities to use memory elements to perform computations that would replace combinational logic processing of a given function. In this research, a computational model based on stored logic is described and interesting issues concerned with memory utilization in processing are analyzed. A small functional unit based on these notions is presented. [ABSTRACT FROM AUTHOR]