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Contact level is the first metal (usually tungsten) connection level between the device and the aluminum or copper interconnects. Depending on the device type (CMOS, memories, photonic device) and technology node, contact patterning is in constant development to improve performance. At the contact cleaning step, we face many new challenges due to the metal or sensitive material exposure with the cleaning chemistry, the decrease of nominal dimensions and the increase of aspect ratio. In particular, new contact clean processes were developed for CMOS devices (28 nm and 14 nm nodes), and photonic devices, in order to be compatible with metal gate or germanium photodiode. In this study, we will compare the efficiency of these new cleaning processes with standard contact clean previously used for CMOS devices from 90 nm down to 45 nm nodes. We will also highlight cleaning efficiency in high aspect ratio structures, and optimized IPA drying capability on a single wafer cleaning tool.

International audience; We present an 802.15.4 compatible transceiver that operates without any off-chip frequency reference. With integrated Cortex-M0, the chip can also transmit BLE beacons with only three external connections (power, ground, and antenna). The RF transmitter operates with >10% system efficiency at-10 dBm output power from a regulated supply. The entire chip, including the microprocessor, can operate below 1 mW peak power when transmitting. The analog receiver power consumption is 1.03 mW from a 1.5V battery.

Wet processing with low oxygen content may provides some advantages, however, full control to avoid oxygen uptake during wafer processing remains a challenge for short process industrialization on single wafer tool. Inline oxygen concentration monitoring was used for process optimization. Then, cobalt etch in diluted HF solutions was evaluated depending on the recorded oxygen concentration and hardware available options for atmosphere control in the process chamber.

Microwire and microelectrode arrays used for cortical neural recording typically consist of tens to hundreds of recording sites, but often only a fraction of these sites are in close enough proximity to firing neurons to record single-unit activity. Recent work has demonstrated precise, depth-controllable mechanisms for the insertion of single neural recording electrodes, but these methods are mostly only capable of inserting electrodes which elicit adverse biological response. We present an electrostatic-based actuator capable of inserting individual carbon fiber microelectrodes which elicit minimal to no adverse biological response. The device is shown to insert a carbon fiber recording electrode into an agar brain phantom and can record an artificial neural signal in saline. This technique provides a platform generalizable to many microwire-style recording electrodes.

In the spring of 2017, the UC Berkeley department of EECS introduced an innovative new course: "28nm SoC for IoT." This course went far beyond schematic-level design typical of circuits education and resulted in a chip going out for manufacturing. Ten students with no prior IC experience, nine undergraduate and one graduate, designed and laid out an SoC in ST 28nm FD-SOI CMOS including a 2.4GHz transceiver, baseband filtering, ADC, Bluetooth MAC, a RISC-V CPU, and internal power regulation. The transceiver, baseband, ADC, and power regulation were successfully fabricated. This paper discusses the instructors' experiences and results with this course.

Si3N4 is widely used in the semiconductor industry as a sacrificial etch stop layer, implantation spacers, hard mask for selective epitaxy. Si3N4 is resistant to many RIE process, to fluoridric acid, and can be easily removed thanks to hot phosphoric acid with excellent selectivity to other materials (Si and SiO2). However hot phosphoric process presents majors drawbacks: Done in wet benches, the levels of metallic and particular contamination, process uniformity, do not match all the requirements of 14nm node and beyond. Surface preparation standards indeed converge towards single wafer cleans for these reasons. But typical etch rate with hot phosphoric are too low (>1Å/min) to be compatible with a single wafer approach. Plasma removal is a possible alternative, either by RIE or CDE (Chemical Downstream Etching). If the selectivity to the SiO2is usually very low for RIE (~15), selectivity for CDE reactors up to 60 have been reported in the last years, increasing the interest for this technique. In the present work we evaluated the etching selectivity of a new CDE process. We achieved successfully its integration in replacement of hot phosphoric acid for a process step denoted as nitride pull back (NPB): In VLSI circuits, transistors are electrically insulated by trenches filled with SiO2. As the filling is done by conformal deposition methods, it is greatly facilitated by an etch back of the top Si3N4 (fig.1). One problem in this case is that CDE used here could etch the silicon in the trench very quickly: this disadvantage has been overcome by oxidizing the flanks of the trench with a RTP process. In this configuration, a SiO2 liner is formed at the surface of the trench. However RTP process is known to create also an oxidized layer at the surface of the Si3N4 that can delay the etching. In this context we evaluated the selectivity of the process on full sheet layers. For that purpose we generated SiN layers made by LPCVD furnace at 770°C, and thermal SIO2 made by RTP. Top of the Si3N4layers were also oxidized to evaluate the etching delay induced by this surface oxidation. Fig2. reports the Si3N4 and SiO2 etch rates vs. etching time. Si3N4 removal rate is very stable around 150 Å/min. In the same time SiO2 etch rate increases moderately form 0.6 to 1.6 Å/min. As a result, the average selectivity is always higher than 100:1 and reaches 250:1 at the early stage of the process. If oxidized, an etch delay is induced and Si3N4 etch rates and selectivity to SIO2 drops rapidly with the oxidation budget (fig.3): Thus a moderate oxidation has been done on the patterned wafer to preserve both Si3N4 etch rate and the liner integrity. Thickness measurements returned a Si3N4 removal of 120Å with a good within wafer uniformity (3.5%), and a negligible SIO2 removal (3N4 etching. Differences of etch rates between dense and isolated areas have been evaluated as far as the defectivity aspects and will be discussed in the full paper.

Today the IC manufacturing faces lots of problematics linked to the continuous down scaling of printed structures. Some of those issues are related to wet processing, which are often used in the IC manufacturing flow for wafer cleaning, material etching and surface preparation. In the current work we summarize the limitations for the next nodes of wet processing such as metallic contaminations, wafer charging, corrosion and pattern collapse. As a replacement, we promoted the isotropic chemical dry etching (CDE) which is supposed to fix all the above drawbacks. Etching steps of SI3N4 layers were evaluated in order to prove the interest of such technique.

TiN Hard Mask (TiN-HM) integration scheme has been widely used for BEOL patterning in order to avoid ultra low-k (ULK) damage during plasma-ash process [1]. As the technology node advances, new integration schemes have to be used for the patterning of features below 80 nm pitch with 193 nm immersion lithography. In particular, thicker TiN-HM is necessary in order to ensure Self-Aligned-Via (SAV) integration which resolves via-metal short yield and TDDB issues caused by Litho-Etch-Litho-Etch (LELE) misalignment [2, 3]. The Cu filling process is significantly more difficult if the thick TiN is not removed because of the high aspect ratio of the structures. Moreover, with the use of TiN hard mask, a time-dependent crystal growth (TiCOF) residue may forms between line etch and metal deposition [4, 5], also hindering copper filling. Post-Etch-Treatment after line etching is one solution to the problem but N2plasma is not efficient enough to suppress the residue completely [6], and the CH4treatment proposed in [5] may be difficult to implement for 14 nm node, thus an efficient wet strip and clean provides a better solution.

Titanium Nitride metal hard mask was first introduced for BEOL patterning at 65 nm [1] and 45 nm nodes [2]. Indeed, in this “Trench First Hard Mask” (TFHM) backend architecture, the dual hard mask stack (SiO2 & TiN) allows a minimized exposure of ULK materials to damaging plasma chemistries, both for line/via etch sequence, and lithography reworks operations. This integration scheme was successfully used for a BEOL pitch down to 90 nm for the 28 nm node, however, for the 14 nm technology node, 64 nm BEOL minimum pitch is required for the first metal levels. Because it is unable to resolve features below 80 nm pitch in a single exposure, conventional 193 nm immersion lithography must be associated with dual patterning schemes, so called Lithography-Etch-Lithography-Etch (LELE) patterning [3] for line levels and self-aligned via (SAV) process [4] for via patterning. In both cases, 2 lithography/etch/clean sequences are necessary to obtain one desired pattern, and associated reworks also become more challenging since first pattern is exposed to resist removal processes (plasma + wet clean). The reference wet cleans that were developed for 65 to 28 nm TiN hardmask patterning, utilizes commonly used chemistry for BEOL post-etch cleans, i.e. diluted hydrofluoric acid (dHF) followed by deionized water Nanospray (DIWNS) on 300 mm single wafer tool.

A unique gate stack solution has been found in gate-first FDSOI to meet at the same time high performance, low leakage, V T centering and reliability criteria for NMOS and PMOS with T inv =12.5A and 14A, respectively. Trade-offs between those characteristics are highlighted in this paper through process knob variations, including the interfacial layer (IL) formation, the IL surface treatment and the drive-in anneal temperature. The path allowing the construction of both low-V T high speed logic, reaching 7.2ps/stg FO3 ring oscillator delay at V nom =0.8V, and high-V T low leakage SRAM, achieving 3pA/cell standby leakage at V nom =0.8V, is demonstrated through gate workfunction engineering and gate leakage optimization. On top of this result, 5 years BTI and 10 years TDDB reliability lifetime were qualified at V max =0.945V, 125°C.

In the frame of the 40nm technology node development, Ni(Pt)Si abnormal diffusion, usually called NiSi encroachment is studied through voltage contrast electron beam inspection. A typical mapping is found for 300mm-Si(100) wafers which is related to NiPt deposition asymmetry, in active zones, between two transistor gates. This observation is related to ''gate shadowing effect'', which induces thinner NiPt thickness and then lower Pt amount at the edge of active zones. TEM analyses of the local NiPt thickness and electrical characterizations as junction leakage permit to determine the minimum of NiPt thickness and/or Pt amount needed to guaranty an adequate NiSi stability.

The MOSFET gate length reduction down to 32nm requires the introduction of a metal gate and a high-K dielectric as gate stack, both stable at high temperature. Here we use a nanometric layer of Lanthanum to shift the device threshold voltage from 500mV. Because this layer plays a key role in the device performance and strongly depends on its deposition process, we have compared two LaO"x deposition methods in terms of physical properties and influence on electrical NMOS device parameters. Chemical characterizations have shown a different oxidization state according to Lanthanum thickness deposited. It has been related to threshold voltage shift and gate leakage current variations on NMOS transistors. Furthermore mobility extractions have shown that Lanthanum is a cause of mobility degradation.

The stability of nickel-based silicides integrated in CMOS circuits has been studied. The evolution of transistor electrical failures is then reported, linked to Ni abnormal migration through different process steps. We have found in our studies that Ni encroachment is not only due to NiSi"2 clusters formation but also to NiSi precipitates formation. Silicon substrate doping, surface preparation, nickel film thickness and the thermal treatments were identified to modify occurrences of this randomly localized phenomenon. Ni-rich phase initial formation is preferable to prevent Ni encroachment even though other upstream process steps for CMOS integration are also key for Ni migration control.

The oxidation of nickel silicide during selective wet etch is investigated for stable contact resistance. This paper describes chemical reactions of nickel–platinum alloy silicide during selective wet etch used to remove unsilicided Ni(Pt). These reactions depend on the nature of silicide phases and selective etch process parameters. For silicide formation conditions such as silicidation temperature, a silicon oxide layer is observed after selective wet etch, replacing nickel silicide layer formed during the first thermal treatment. The mechanism of oxide formation and growth related to the interaction between selective wet etch chemistries and Ni(Pt) silicidation is then discussed. Thanks to the monosilicide phase formation this detrimental phenomenon can be prevented.

Nickel based silicide films were prepared by annealing nickel-platinum layers deposited on n doped Si substrates. We report on the evolution of the phase formation and the redistribution of contaminants on blanket wafers during silicide formation as a function of the nitrogen gas flow introduces during Ni(Pt) deposition. Nitrogen incorporation creates a contamination as-deposited layer which modifies phase formation and changes nickel diffusion. Nitrogen is not incorporated in silicide formed. After a second anneal, the monosilicide forms excepted for high nitrogen quantity introduced where the Ni"3Si"2 is always observed. Monosilicide thermal stability is also improved by nitrogen co-plasma.

Nickel based silicide films were prepared by annealing nickel-platinum layers deposited on n-doped Si substrates. We report on the evolution of the crystallography, the phase formation and the redistribution of contaminants on blanket wafers during silicide formation as a function of the silicon surface preparation prior to Ni(Pt) deposition. In situ argon sputtering etch creates a contamination layer which modifies phase texture during the formation of the first Ni silicide phases. Using remote pre-clean results in a predominant Ni"2Si phase with preferential grain orientation after a first anneal. After a second anneal, the monosilicide forms, regardless of what nickel rich silicide phase was initially formed and regardless of the surface preparation prior to metal deposition.

session C2L-E: Advanced CMOS Device and Technology; International audience; In this paper, the impact of metallic lanthanum (La) deposited by Radio-Frequency PVD on effective work function (WF eff ) of HfON-based NFET devices in a sacrificial metal gate-first approach is evaluated for the first time. Engineering of WF eff towards N+ without leakage degradation is demonstrated by tuning both the pedestal TiN thickness and the as-deposited metallic La dose. WF eff shift is related to a La-induced interfacial dipole (5), whose value has been correlated to the effective La dose into HfON/SiON stack after diffusion annealing, which has been accurately measured through a spectroscopic method based on La X-Ray Fluorescence (XRF).

In this paper, wet cleaning solution compatible with cobalt are investigated to achieve low Co etching rate on blankets film and no film attack on patterned 14nm wafer after line and via etching. Proposed solutions are compared to conventional wet cleaning solutions [5],[6].

A complete analysis of HfO2 high k thin layers deposited by metal organic chemical vapour deposition (MOCVD) is made by infrared spectroscopy using different optical configurations. Multiple internal reflection (MIR) and attenuated total reflection (ATR) are used, giving information about morphology and composition of the layers. Samples under investigation are HfO2 layer of 3 to 12 nm thick deposited at 400 and 550 °C on thin silicon oxide. MIR technique elucidates carbon content in the layer and ATR informs about the interface evolution, and the crystalline character of the HfO2 layer. The high sensitivity of MIR coupled with the large spectral range available of ATR allow the full characterisation of these layers. (© 2003 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back bias (FBB) we experimentally demonstrate that the power efficiency of this technology provides an additional 40% dynamic power reduction for ring oscillators working at the same speed. Finally, a full single-port SRAM offering is reported, including an 0.081°m 2 high-density bitcell and two 0.090°m 2 bitcell flavors used to address high performance and low leakage-low Vmin requirements.

In plane-electronic transport in UHV Co(32 A)/Ru(x A)/Co(32 A) sandwiches is analyzed with particular attention paid to the role of interface mixing on the moment and the giant magnetoresistance (GMR) effect. The resistivity measurements show that the GMR is very small in these sandwiches due to the presence of intermixed CoRu alloy at the interfaces. The magnetic profile of this mixed interface has been determined by ab initio DFT-LDA calculations which show two different regions. Magnetic and non-magnetic regions which are centers of spin-dependent and strong spin-independent scattering, respectively, reduce the flow of polarized electrons from one ferromagnetic layer to the other. This intermixed interface has been successfully included in our GMR simulation using a semi-classical description of the two spin channel currents to reproduce the experimental results.

The contribution of conduction electron scattering to magnon relaxation in Permalloy thin films [2-20 nm] was studied by resistivity measurements and by high frequency permeability measurements using network analyzer ferromagnetic resonance. Both effective Gilbert damping alpha of the magnetization and electrical resistivity rho were measured from room temperature down to 10 K. We observe that an increase of the resistivity does not necessarily lead to an increase of the effective damping. Indeed, increases up to 50% of the resistivity in the studied temperature range are not accompanied by any change of the damping parameter alpha. We discuss our findings by sorting out the different conduction electron scattering channels that lead to spin-flip, and that hence contribute to the overall damping. We conclude that alloy disorder scattering is the main channel that leads to correlated contributions to damping and resistivity

The interlayer coupling in Co/Rh/Co sandwiches prepared by UHV evaporation has been investigated by means of magnetization and transport experiments. We found that the antiferromagnetic coupling strength for thin Rh layers is the largest ever obtained in magnetic systems, reaching approximately 34 erg/cm2 for 5 A thick Rh interlayer. This value is 7 to 8 times larger than the highest value previously observed in the Co/Ru system prepared under similar conditions. This unexpectedly large difference in the coupling strength between these two systems is mainly due to the magnetic nature of the interfaces. This is further supported by ab initio calculations of the magnetic moments in superlattices with mixed interfaces.

A study of the exchange coupling of Co/Rh/Co sandwiches grown by ultrahigh-vacuum evaporation on mica substrata is presented. In these sandwiches, both Co and Rh layers have a (111) fcc structure, as indicated by the RHEED pattern observed during growth. Oscillatory indirect exchange coupling and magnetoresistance as a function of the Rh thickness a observed. The most interesting result is the very strong antiferromagnetic exchange coupling reached for thin Rh space layers: 34 erg/cm 2 for 4.8 A Rh. We attribute this result partly to the nature of the magnetic/non-magnetic interfaces shown by magnetisation measurements. Indeed, no reduction in the Co moment is found for these sandwiches although the is a large interdiffusion is expected at their interfaces. This is confirmed by ab initio calculations of the magnetisation with mixed interfaces. Such a magnetic nature of the interfaces should be favourable for electronic confinement in the space layer.

A magnetoresistive GMR sensor scheme for detection of angular positions is demonstrated and analyzed in which the hard magnetic layers are replaced by artificial antiferromagnetic subsystems (AAFs). These consist of ferromagnetic layers (Co) that are antiferromagnetically coupled via interlayers (Cu or Ru). The rigidity of this AAF is improved by an order of magnitude as compared to the individual Co layers. Operational field windows for 360° angle detectors of 15–20 kA/m have been realized. The maximal sensor signal Δϱ/ϱ is 6%. The temperature operation range extends up to 150°C. The angle resolution is about 1°.

A magnetization model is presented that is used to cover trilayers containing two magnetic layers that are exchange coupled via an intermediate nonmagnetic layer and that have different crystalline anisotropies. The interfaces are coupled to the bulk by a twisted magnetization configuration which is evaluated using the Ritz method. By minimizing the total energy, experimental magnetization curves of strongly coupled Co/Ru sandwiches can be reproduced with a good precision and with the same set of parameters in two perpendicular field directions. These physical parameters can be determined with a good reliability and are in agreement with the literature except for the bulk anisotropy of the Co layer first deposited, which is twice as large as the known bulk value. This originates in the magnetoelastic contributions due to lattice misfit and interface roughness. It is shown that the interlayer exchange coupling forces the magnetization of both layers to be along the same axis in the low‐field range notwithstanding the opposite sign of the anisotropy constants in most stacks. It is also demonstrated that the differences in the orientations of the moments in one Co layer are modest and depend on the various parameters. In particular, the bulk exchange constant is a decisive parameter that makes the calculated curves close to the experimental ones.

This paper presents a cost-effective 45-nm technology platform, primarily designed to serve the wireless multimedia and consumer electronics needs. This platform features low power transistors operating at a nominal voltage of 1.1V, an ultra low k dielectric (k~2.5) with up to 9 Cu metal layers and 0.25/0.3/0.37mum2 SRAM cells. This platform also features an optional third gate oxide for either higher speed or active power mitigation. This technology has been developed on the (100)-oriented substrate with a key focus on process simplicity. Transistor improvement relies on mask-free strain engineering techniques along with co-implanted halos and laser anneal. The impact of laser anneal on transistor reliability and mixed-signal capabilities are also examined. Drive current as high as 660/320 muA/mum at 1nA/mum and 1.1V are reported

In the linear regime, a measure of the magnetic damping can be obtained from the linewidth of the ferromagnetic resonance peak. One means of distinguishing between different classes of damping mechanisms is to examine the frequency dependence of the linewidth. With network analyzer ferromagnetic resonance (NA-FMR), the magnetic susceptibility can be measured in the 0-26 GHz range, from which one can obtain valuable information about how energy dissipation evolves at higher frequencies. The NA-FMR does, however, present a number of caveats. Under certain resonance conditions, for example, it is possible that non-uniform spin-wave modes are excited, due to a driving magnetic field that will be necessarily non-uniform when viewed by a sample whose dimensions exceed those of the central conductor of the coplanar wave guide. This results in the excitation of spin waves, which cause broadening of the resonance peak and then an apparent enhancement of the measured linewidth. We analyze quantitatively the contribution of this experimental source of error and show how to extract the value of the "intrinsic" damping.

This study aims to determine the role of electron scattering in the damping mechanisms of magnetization and electrical resistivity of Permalloy thin films at varying temperatures. The complex dynamic susceptibility of the magnetic thin films are measured using ferromagnetic resonance technique. The resistivity follows a quadratic law with temperature which is attributed to electron-electron and electron-magnon scattering in the metallic magnetic materials.

Low-resistance magnetic tunnel junctions with an $\mathrm{Mg}\mathrm{O}\text{\ensuremath{-}}{\mathrm{Al}}_{2}{\mathrm{O}}_{3}$ composite tunnel barrier have been grown. From the theoretical point of view, current-voltage and magnetoresistance-voltage characteristics are predicted to be asymmetric. These asymmetries are studied as a function of barrier thicknesses for given experimental MgO and ${\mathrm{Al}}_{2}{\mathrm{O}}_{3}$ barrier heights. From an experimental point of view, the bottom alumina barrier acts as a diffusion barrier allowing the complete oxidation of the thin deposited Mg layer. As a result, composite ${\mathrm{Al}}_{2}{\mathrm{O}}_{3}∕\mathrm{Mg}\mathrm{O}$ tunnel barriers show a lower area resistance and a magnetoresistance signal at nonzero applied voltage that is predicted to be equivalent as single ${\mathrm{Al}}_{2}{\mathrm{O}}_{3}$ tunnel barriers with the same total thickness. Current-voltage and magnetoresistance-voltage characteristics are shown to be asymmetric at high voltages.

A 90nm magnetoresistive random access memory (MRAM) based on the toggle switching mode has been successfully demonstrated for the first time in a 90nm CMOS process. The MRAM memory cell is based on a 1-transistor 1-magnetic tunnel junction (1T1MTJ) with 0.29/spl mu/m/sup 2/bit cell. The results of the 4k bit array demonstrate scalability of MRAM to 90nm technology.

Hf-family compounds have been widely studied as high k gate dielectric materials, they can be elaborated in a wide range of deposition techniques but ALD and MOCVD are the most advanced. In this contribution, the deposition of pure HfO2 is performed by Atomic Vapour Deposition, which is a sort of pulsed-mode MOCVD. The precursor, diluted into a solvent, is pulsed through specific injectors (TriJet®), micro-droplets are vaporised and distributed to the substrate through a showerhead. ATR-FTIR and Hg-probe measurements have been extensively used to evaluate the materials. The advantage of this specific MOCVD system is that it allows working within a wide range of liquid injection frequencies. Thus, we have been able to show that the frequency of injection has a huge impact on the structural and electrical properties of the material. It has been evidence that working at low frequencies is crucial in order to get good electrical behaviour. Higher temperature deposition shows also a clear benefit. An EOT of 1.15 nm with 6.10−2 A/cm2 at |Vfb| + 1 V, that is to say about 3 orders of magnitude below what is obtained with SiO2 has been obtained on capacitors with TiN gate. This is a very good achievement fore pure HfO2 deposited by MOCVD.This work has been made in the frame of MEDEA + T207 European project with the help of Air Liquide and Epichem.

Evidence is given of a strong dependence of magnetoresistance on temperature in Co/Ru sandwiches. This dependence while weak for thin Ru layers is much stronger for thicker Ru layers. In fact, three oscillations in saturation magnetoresistance and saturation field as a function of the thickness of the Ru layer tRu are observed at 4.2 K while only one oscillation is found at 300 K. In addition, for thin Ru layers, tRu≤11 A, the saturation magnetoresistance is found to decrease between 4.2 and 300 K. In contrast, for Ru thickness in the range 11 A≤tRu≤14 A, the behavior is reversed, leading to the increase of the magnetoresistance at 300 K. This behavior is attributed to the spin disorder occurring at the interfaces at room temperature. Finally, for tRu≥14 A the magnetoresistance completely vanishes at 300 K while a relatively high value is still observed for large Ru thickness, tRu=80 A, at 4.2 K. This indicates that the mean free path of the conduction electrons in the Ru layer is strongly reduced from ab...

The dynamic susceptibility of Permalloy films was measured using network analyzer ferromagnetic resonance, in order to study the broadband behavior of the damping parameter. The susceptibility is extracted from the transmission coefficient of a microwave propagating through a waveguide loaded by the magnetic sample. At low frequencies, the period of the microwave is much greater than the propagation time through the waveguide. The impedance due to the magnetic film is localized, and can be treated by simple signal theory. However, at high frequencies, the extracted signal can be significantly distorted by propagation effects. Here we present calculations taking into account the effect of the propagation, and show how to correct experimental data

The authors present results on current induced domain wall motion in Co∕Cu∕CoFeB trilayered stripes. The threshold current densities are around 106A∕cm2 at zero field, i.e., about two orders of magnitude smaller than in single NiFe stripes. The domain wall motion is assisted when the field torque acts in the same direction as the spin torque. When the field torque is opposed to the spin transfer one and above a threshold field, the authors observe a reversible displacement of the domain wall (peak in the dV∕dI measurements). This can be ascribed to the onset of domain wall fluctuations, which is confirmed by micromagnetic simulations.

A study of the indirect exchange coupling of Co/Ru sandwiches for small Ru spacer thicknesses has been performed. For critical thicknesses of the spacer, a large curvature of the M - H loops can be observed and its origin lies in a competition between areas with different couplings. These areas are smaller than the magnetic coherence length of the cobalt layers, and the existence of a large extrinsic biquadratic coupling is likely to occur. A strong interdiffusion at the interfaces seems to be determinant for the coupling mechanism.

The effect of the number of periods on the magnetoresistance (MR) has been investigated on [Co 32A Ru x A ] N superlattices, with N = 2 for sandwiches and N = 10 for multilayers. MR values obtained for multilayers are larger than those found for sandwiches at both 4.2 and 300 K. This effect is attributed to the conduction electrons which are scattered by several interfaces in multilayers, while they are scattered by just one interface in sandwiches. However, the exchange coupling is sensitively reduced between multilayers and sandwiches at room temperature, while no significant change is observed at 4.2 K.

The structural, magnetic and transport properties of Co/Rh sandwiches grown by ultra high vacuum evaporation and sputtering have been studied. High-energy electron diffraction observations during the growth reveal that both Co and Rh layers have been stabilised in the (111) fcc structure for the evaporated sandwiches. X-ray measurements performed on sputtered samples show a predominant fcc polycrystalline structure of the stacks with a preferential (111) texture. Magnetisation and magnetoresistance measurements show a very strong antiferromagnetic exchange coupling for thin Rh layers, reaching for 4.8A Rh, the strongest ever observed in exchange coupled systems. This value is in good agreement with the value of obtained by ab initio calculations for Co/Rh (hcp) superlattices. This is explained by the magnetic nature of the Co/Rh interfaces. Indeed, the variation of the measured saturation magnetisation as a function of the Co layer thickness shows no evidence of Co moment reduction for the Co atoms located at the interfaces, even for the very thin layers. The value of the preserved magnetic moments of the cobalt atoms at the interfaces is confirmed by ab initio calculations for Co/Rh superlattices taking the intermixing into account.