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An optimal device structure for integrating bipolar and CMOS is described. Process design and device performance are discussed. Both the vertical n-p-n and MOS devices have non-overlapping super self-aligned (NOVA) structures. The base-collector and source/drain junction capacitances are significantly reduced. This structure allows complete silicidation of active polysilicon electrodes, cutting down the parasitic resistances of source, drain, and extrinsic base. The critical gate and emitter regions are protected from direct reactive ion etching exposure and damage. All shallow junctions are contacted by polysilicon electrodes which suppress silicide-induced leakage. An arsenic buried layer minimizes collector resistance and collector-substrate capacitance. A novel selective epitaxy capping technique suppresses lateral autodoping from the arsenic buried layer. Fully recessed oxide with polysilicon buffer layer is used to achieve a low defect density device isolation. CMOS with L/sub eff/=1.1 mu m and W/sub n//W/sub p/=10 mu m/10 mu m exhibits averaged ring oscillator delay of 128 ps/stage. An n-p-n transistor with f/sub T/, of 14 GHz and low-power emitter-coupled logic ring oscillator with a delay of 97 ps/stage have been fabricated. >

BiCMOS technology which merges optimal CMOS and bipolar device structure is reported. Based on a nonoverlapping super-self-aligned structure (NOVA), the latest 1.5- mu m CMOS and ECL (emitter-coupled logic) ring oscillators have minimum delays of 110 ps/stage and 87 ps/stage, respectively. A frequency divider operating up to 4.6 GHz has been fabricated. A multiplexer and demultiplexer function up to 5.1 Gb/s. In addition to double self-alignments, a unique epi/isolation scheme combining lateral autodoping free epi deposition with a new fully recessed oxide process have been developed. This approach significantly simplifies the isolation process and is an important factor in achieving high speed with a conservative 1.5- mu m design rule. >

It is demonstrated that high-speed bipolar and CMOS processes can be merged without compromise on either device. A NOVA (nonoverlapping super self-aligned) structure with an advanced epi/isolation process that reduces parasitic capacitances and resistances is reported. The scheme combines lateral autodoping free epi deposition with a novel fully recessed oxide process. This approach significantly simplifies the isolation process and is an important factor in achieving high speed with a conservative 1.5- mu m design rule. A high-speed frequency divider, a multiplexer, and a demultiplexer operating up to 4.1 GHz, 5.5 Gb/s, and 6.2 Gb/s, respectively, have been fabricated. The results show that NOVA BiCMOS is suitable for Gb/s digital VLSI application. >

An effective way to suppress lateral autodoping from the heavily arsenic-doped buried layer during silicon epitaxy is described. By using this simple technique, collector-substrate capacitance (C/sub cs/) is minimized. This process is ideal for high-speed BiCMOS and bipolar technology. A thin epilayer is first grown selectively on the buried layer. This selectively grown film suppresses the release of arsenic during the subsequent epi growth. High-performance bipolar devices have been fabricated in this epi material. Electrical measurements indicate that the crystalline quality is excellent. >

Integrated digital test circuits, as well as discrete NMOS devices, have been fabricated in epitaxial layers produced by silicon molecular-beam epitaxy (Si-MBE). The performance of these circuits and devices was found to be very similar to that of identical components processed in standard substrates. Unusually high low-field mobility was measured in the MBE MOSFET's.

An experimental study of the p-type ion dopant BF 2 + in silicon molecular beam epitaxy (MBE) is described. BF 2 + was used to dope MBE layers during growth to levels ranging from 1 × 1016/cm3to 4 × 1018/cm3over a growth temperature range of 650°C to 1000°C. The layers were evaluated using spreading resistance, chemical etching, and secondary ion mass spectroscopy. Complete dopant activation was observed for all growth temperatures. Remnant fluorine in the epitaxial layer was less than 2 × 1016/cm3in all cases. Diffused p-n junction diodes fabricated in BF 2 +-doped epitaxial material showed hard reverse breakdown characteristics.

An ideal device structure for integrating bipolar and CMOS is reported in this paper. Both the vertical npn and MOS devices have new non-overlapping super self-aligned structures. With a single 5V supply, averaged per stage delay of 82ps and 125ps have been measured for 0.6µm and 0.85µm (L eff ) CMOS ring oscillators. Bipolar transistors have also been fabricated with a nominal current gain of 100.