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A low-power transmitter driver for chiplet interconnection was designed and experimentally implemented based on the interchip interconnection standard proposed by the UCIe protocol. The driver circuit adopts a source series terminated (SST) diver, whose power consumption is only 1/4 that of the current mode logic (CML) structure. In add-on, based on adjustable feedforward equalization technology, the driver circuit adjusts the equalization strength for different channel attenuations. By de-emphasizing equalization, it enhances the quality of the transmitted signal, ultimately reducing inter-symbol interference. This circuit was designed under CMOS 28 nm process. The front-end simulation results show that the maximum equalization intensity is --3. 7 dB when the 0. 9 V voltage is supplied. When the 32 Gbps NRZ signal passes through the 21 mm channel (the attenuation at the 16 GHz Nyquist frequency is --2. 37 dB), after adjusting the appropriate equalization intensity, the eye height of the output waveform eye diagram is 253 mV (71.8%), the eye width is 27 ps (87%), and the simulation power consumption is only 4. 0 mW. [ABSTRACT FROM AUTHOR]

Multicarrier modulation, while providing a theoretical pathway to data rates approaching the Shannon limit and being extensively utilized in wireless communication, has encountered limited application in high-speed wireline communication. This limitation is primarily due to substantial large amplitude peaks, which necessitates a reduction in the signal’s power levels to circumvent signal clipping. This, in turn, results in a low signal-to-noise ratio (SNR) which puts these modulations at a serious disadvantage compared to conventional modulation schemes. This work proposes a novel companding solution in the design of the Continuous Time Linear Equalizer (CTLE) alongside nonlinear blocks to reduce Peak to Average Power Ratio (PAPR), therefore improving the overall link performance. This paper presents a PAPR reduction technique and its implementation in the receiver, distinguishing it from previous studies that place the compander at the transmitter where it fails to work in the presence of an Inter-Symbol Interference (ISI) channel. A theoretical study as well as an implementation of this method is provided, and the merits and performance improvements are demonstrated.

This paper demonstrates the first silicon-verified FBMC encoder and decoder designed to emulate beyond $224Gb/s$ wireline communication. It also compares the performance of FBMC to PAM and DMT in three steps. First, the digital power and area consumption are compared using measured results from the manufactured test chip. Second, the data rate is determined using lab-measured results. And third, the performance when subject to notched channels is analyzed using simulation results. Finally, we present a method to emulate wireline links while reducing the emulator complexity and simulation time by one to two orders of magnitude over conventional over-sampled techniques. Our analysis indicates that given a smooth channel and an SNR which enables an average spectral efficiency of $4bits/sec/Hz$ at a bit-error rate of 10-3, both DMT and FBMC perform similarly to a conventional PAM-4 link. However, when noise is reduced and a spectral notch is applied, thereby achieving an average spectral efficiency of $4.6bits/sec/Hz$ , DMT and FBMC can outperform PAM by 2.1 and 2.3 times, respectively. In addition, we estimate FBMC’s encoder and decoder power consumption at $1.53pJ/b$ and $1.98pJ/b$ , respectively, and area requirement at $0.07mm^{2}$ and $0.17mm^{2}$ , respectively, which is similar to DMT. These values are competitive with similar $22nm$ PAM transceivers, suggesting that DMT and FBMC are viable alternatives to PAM for next-generation high-speed wireline applications.

This paper presents a method to estimate the nonlinearity of the analog data path of Serdes receiver, in real time operation. The estimated nonlinearity can be used to adapt various receiver parameters to improve performance. The proposed method is demonstrated for a 200 Gbps ADC-Based receiver, in which, nonlinearity estimate is used to set Analog Front End (AFE) swing optimally, resulting in improved eye opening. The proposed method is also used to adapt decompressive characteristic optimally.

This paper presents a comprehensive study of noise prediction and cancellation techniques in high-speed wireline communication systems. Feedforward and feedback architectures are compared, and it is found that while feedforward architecture can reduce total noise power, it fails to reduce symbol error rate (SER) due to unreliable noise estimation. To address this issue, an optimal noise estimation and cancellation filter (ONECF) is proposed, which directly minimizes SER. The paper provides mathematical analysis and experimental results of ONECF, demonstrating that ONECF is effective in reducing SER and improving SNR, and the degree of improvement is proportional to the channel loss. However, ONECF’s performance saturates at a certain level, which depends on the number of taps used. We conclude that feedforward noise cancelling filters are suitable for low to medium loss channels, whereas feedback ones are suitable for high loss channels.

A new voltage-controlled oscillator (VCO) topology for serializer–deserializer (SerDes) applications is proposed in this paper. The topology is suitable for SATA, PCI Express, and USB 3 protocols. The VCO is based on two-ring oscillator cores and operates in several frequency bands, as required by the corresponding protocol specifications, with a constant VCO gain and improved linear control over the frequency tuning. Additionally, it is supported by an automatic digital compensation mechanism for process variations. The VCO has been designed to cover the several speeds of the SATA and PCI Express protocols, with optimized performance in all of them, including the current consumption, the phase noise, and the frequency tuning in each case. Designed in a CMOS 22 nm technology node with a 0.8 V supply voltage, it can achieve, at 3 GHz frequency, a phase noise better than −90 dBc/Hz at 1 MHz offset and an average power consumption equal to 3.84 mW. Extended digital control can set optimized configurations for phase noise, current consumption, and VCO gain vs. process variations. Extensive post-layout simulation results verify the superior performance. [ABSTRACT FROM AUTHOR]

As the PCIe 6.0 specification places higher requirements on signal integrity and transmission latency, it becomes especially important to improve signal transmission performance at the physical layer of the transceiver interface. Retimer circuits are a key component of high-speed serial interfaces, and their delay and jitter size directly affect the overall performance of PCIe. For the typical retimer circuit with large-latency and low-jitter performance, this paper proposes a low-latency and low-jitter Retimer circuit based on CDR + PLL architecture for PCIe 6.0, using a jitter-canceling filter circuit to eliminate the frequency difference between the retiming clock and data, reduce the retiming clock jitter, and improve the quality of Retimer output data. The data are sampled using the retiming clock and then output, avoiding the problem of large penetration latency of typical retimer circuits. The circuit is designed using the CMOS 28 nm process. Simulation results show that when 112 Gbps PAM4 data are input to the retimer circuit, the Retimer penetration latency is 27.3 ps, which is 83.5% lower than the typical Retimer structure; the output jitter data are 741 fs, a 31.4% reduction compared to the typical retimer structure. [ABSTRACT FROM AUTHOR]

Wireline receivers continue to target higher data rates, posing great challenges at circuit and architecture levels. Governed by tradeoffs among speed, power consumption, and channel loss (CL), receiver designs can benefit from new methods that push the performance envelope. This paper presents a number of techniques that allow non-return-to-zero data rates as high as 40 and 56 Gb/s in 45-nm and 28-nm CMOS technologies, respectively. The prototypes operate with a CL of 19-25 dB and a bit error rate of less than 10−12.

Adiabatic quantum-flux-parametron (AQFP) logic is an ultra-low-power superconductor logic family. AQFP logic gates are powered and clocked by dedicated clocking schemes using ac excitation currents to implement an energy-efficient switching process, adiabatic switching. We have proposed a low-latency clocking scheme, delay-line clocking, and demonstrated basic AQFP logic gates. In order to test more complex circuits, a serializer/deserializer (SerDes) should be incorporated into the AQFP circuit under test, since the number of input/output (I/O) cables is limited by equipment. Therefore, in the present study we propose and develop a novel SerDes for testing delay-line-clocked AQFP circuits by combining AQFP and rapid single-flux-quantum (RSFQ) logic families, which we refer to as the AQFP/RSFQ hybrid SerDes. The hybrid SerDes comprises RSFQ shift registers to facilitate the data storage during serial-to-parallel and parallel-to-serial conversion. Furthermore, all the component circuits in the hybrid SerDes are clocked by the identical excitation current to synchronize the AQFP and RSFQ parts. We fabricate and demonstrate a delay-line-clocked AQFP circuit (8-to-3 encoder, which is the largest delay-line-clocked circuit ever designed) integrated with the hybrid SerDes at 4.2 K up to 4.5 GHz. Our measurement results indicate that the hybrid SerDes enables the testing of delay-line-clocked AQFP circuits with only a few I/O cables and is thus a powerful tool for the development of very large-scale integration AQFP circuits.

This paper proposes a novel design for Maximum Likelihood Sequence Estimation (MLSE) used in ultra-high-speed wireline communication. We take advantage of the propagated errors caused by Decision-Feedback Equalizer (DFE) to activate and guide the MLSE, thereby reducing its complexity. The design is customized for a 4-PAM, 1 + D signaling system, and synthesized in 16nm FinFET TSMC Technology. For comparison purposes, a conventional MLSE is also synthesized in the same technology. The synthesis report confirms that the proposed design consumes 1/10 of the power and occupies 1/15 of the area required by the conventional MLSE while having a comparable bit error rate.

This article presents a pulse-amplitude-modulated (PAM)-8 wireline transceiver with receiver-side pulsewidth-modulated (PWM) or time-domain-based feedforward equalization (FFE) technique. The receiver converts the voltage-modulated signals or PAM signals into PWM signals and processes them using inverter-based delay elements having a rail-to-rail voltage swing. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity on the receiver. The proposed PAM-8 transceiver can operate from 12.0 to 39.6 Gb/s and compensates 14-dB loss at 6.6 GHz with an efficiency of 8.66 pJ/bit in 65-nm CMOS. [ABSTRACT FROM AUTHOR]

Wireline transmitters operating at tens of gigabits per second pose challenging design issues ranging from limited bandwidths to severe sensitivity to jitter. This paper presents a number of analog and digital circuit techniques that allow data rates as high as 80 Gb/s in 45-nm CMOS technology. A PAM4 prototype delivers an output swing of 630 mV $_{pp}$ with a clock jitter of 205 fs $_{rms}$ while drawing 44 mW.

This paper proposes a discrete multi-tone timing-recovery system with adaptive equalization for ultra-high-speed wireline applications. It combines frequency-domain clock recovery with decision-directed equalization to improve receiver performance while eliminating the need for pilot carriers, thereby increasing spectral efficiency. Compared to a conventional pilot-carrier-based technique employing four pilot carriers and a 32-point FFT, this approach improves phase-error sensitivity by 3.6 times, tracking bandwidth by 1.7 times, increases the jitter tolerance slope by $20dB$ per decade at low frequency, and removes residual equalization error, resulting in an overall data-rate increase of 27%. The concept is validated at the system-level and gate-level through synthesis in an FPGA. A convergence analysis of both the adaptive equalizer and clock synchronization shows the system’s ability to mitigate error propagation and remain synchronized in the presence of impairments. Finally, we highlight the system’s ability to trade-off clock convergence versus phase error sensitivity. Either parameter can be adjusted by 15 times, optimizing the receiver over a broad range of signal conditions.

This article presents a 200-Gb/s pulse amplitude-modulation four-level (PAM-4) and 100-Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the target data rate, the output bandwidth and swing of the proposed TX are optimized by minimizing the output capacitance of the 4:1 multiplexer (MUX) and driver stage with pull-up current sources and adopting a fully reconfigurable 5-tap feed-forward equalizer (FFE). The key circuit includes a segmented 8:4 MUX and 4:1 MUX/driver, a thermal encoder and retimer, and a flexible clock distribution network. Using the layout generated with Berkeley Analog Generator (BAG), the proposed TX achieves an eye opening with >52.9-mV eye height, 0.36 UI eye width, >98% RLM, and 4.63 pJ/b at 200-Gb/s PAM-4 signaling under >6-dB channel loss at 50 GHz, demonstrating the highest data rate achieved using a planar process. [ABSTRACT FROM AUTHOR]

This article presents analysis, design details, and measurement result of a 224-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter (TX) consisting of a 7-bit voltage digital-to-analog converter (DAC) driver, digital 8-tap feed-forward equalizer (FFE), and a 28-GHz inductively peaked clock distribution network. The TX DAC uses quarter-rate clocking with a 4:1 pulse-based data serialization architecture. Design techniques for generating and distributing low-jitter CMOS clocks up to 29 GHz, timing closure in the serializer, 112-Gbaud 4:1 data MUX using 1-UI pulse generator, and bandwidth/return loss/group delay optimized output pad network using a 9th-order LC filter are described. Fabricated in the Intel 10-nm FinFET process technology, the TX demonstrates random jitter (RJ) of 65 fsrms with nominal output swing of $1.0~V_{\mathrm {ppd}}$ at 224 Gb/s achieving 1.88-pJ/b energy efficiency including an on-die LC phase-locked loop (PLL). To the best of authors’ knowledge, this TX achieved the highest data rate with the lowest RJ for CMOS SerDes TXs reported to date. [ABSTRACT FROM AUTHOR]

The increasing complexity of Internet-of-Things (IoT) applications and near-sensor processing algorithms is pushing the computational power of low-power, battery-operated end-node systems. This trend also reveals growing demands for high-speed and energy-efficient inter-chip communications to manage the increasing amount of data coming from off-chip sensors and memories. While traditional microcontroller interfaces such as SPIs cannot cope with tight energy and large bandwidth requirements, low-voltage swing transceivers can tackle this challenge, thanks to their capability to achieve several Gbps of the communication speed at milliwatt power levels. However, recent research on high-speed serial links focused on high-performance systems, with a power consumption significantly larger than the one of low-power IoT end-nodes, or on stand-alone designs not integrated at a system level. This article presents a low-swing transceiver for the energy-efficient and low-power chip-to-chip communication fully integrated within an IoT end-node system-on-chip, fabricated in CMOS 65-nm technology. The transceiver can be easily controlled via a software interface; thus, we can consider realistic scenarios for the data communication, which cannot be assessed in stand-alone prototypes. Chip measurements show that the transceiver achieves $8.46\times $ higher energy efficiency at $15.9\times $ higher performance than a traditional microcontroller interface such as a single-SPI. [ABSTRACT FROM AUTHOR]

SERDES(serial de-serialization) technology has become the mainstream physical layer specification of high-speed interface due to its high transmission rate and strong capacity of resisting disturbance. However, the upper PCS(physical coding sublayer) needs to set elastic buffering, code, encode and do other functions, so the system transmission delay is high. SERDES cannot be directly applied to delay sensitive applications such as processor direct connection. This paper introduces a design of PCS architecture based on synchronous phase compensation buffer(SPCB), which can be applied to delay sensitive SERDES transmission system. This architecture features high throughput and ultra-low latency. With a custom SPCB, the transmission reception path delay is about 10 ns at 32 Gb/s per lane, which is about half of the typical PCS delay in the industry, reaching the level of Intel(QPI) and AMD(HT) interface. This PCS architecture can be realized through 28 nm/16 nm/7 nm chip manufacturing tech, and has been applied to a variety of domestic processor.

This article describes a 4 × 112 Gb/s digital receiver targeting long-reach (LR) channels. An SNR optimized approach is presented, which relaxes the ADC resolution requirement and the number of FFE taps without sacrificing BER. The discrete-time front end overcomes gain–BW limitations to provide 10+ dB gain at 28 GHz. A 56-GS/s ADC then converts the signal to 6-b digital consuming only 195 mW. The following DFE-FFE-based digital equalizer is capable of compensating 36-dB loss achieving a BER of 2e−5. Furthermore, TDC and ISI filter-based low-latency timing recovery meet jitter tolerance specs over a wide range of data rates from 10 to 112 Gb/s, including 28-Gb/s NRZ. The overall receiver consumes 338 mW with 3.18-pJ/bit energy efficiency. [ABSTRACT FROM AUTHOR]

One of the favorable tools for signal integrity evaluation is eye diagram analysis. This is traditionally performed with a lengthy transient simulation, which can be prohibitively time consuming for complex high-speed channels with a low bit error rate. Methods for eye estimation exist; however, they are either only applicable to linear time-invariant systems or have lack in accuracy or efficiency. In this article, an optimization-based approach is proposed to quickly obtain the worst-case eye diagram characteristics. This approach focuses on the inter-symbol interference since its effect can span over many symbols and include crosstalk, making it challenging to model. In this article, the data patterns leading to the lowest voltage corresponding to a high symbol, the highest voltage corresponding to a low symbol, and the times of minimum and maximum level crossing points are calculated. Then, eye height, eye width, and the worst-case eye opening are estimated using these points. To reduce complexity, the proposed approach includes a mapping algorithm that exploits the Gray code. Additionally, Bayesian optimization is used because of its efficiency and good performance on non-linear and non-convex problems. Finally, the application of the proposed approach to high-speed SerDes channels, and channels in system-on-package designs is evaluated with numerical examples, where the results show its accuracy and efficiency. [ABSTRACT FROM AUTHOR]

This article presents a clock-domain-based integrated pulsewidth modulation (PWM) (iPWM) line-coding scheme to enable equalization while operating at low supply voltages. While conventional equalizers such as feedforward equalizer (FFE), decision feedback equalizer (DFE), and continuous-time linear equalizer (CTLE) are present on the high-bandwidth data path, the proposed iPWM-based line-coding-based approach moved the equalization logic away from the data path and into the subrate clock path. As a result, the proposed clock-domain iPWM line coding can operate at low supply voltages. An energy-efficient implementation of the proposed scheme was demonstrated. Fabricated in a 65-nm CMOS process, the proposed transceiver operates over a data-rate range of 3–16 Gb/s from 0.5 to 0.9 V. Equalization in this transceiver was done using iPWM and a passive CTLE. Operating at 10 Gb/s at 0.65 V, the proposed transceiver is capable of equalizing up to 27 dB of channel loss at energy efficiency of 1.8 pJ/bit. [ABSTRACT FROM AUTHOR]

In the present technology development billions of transistors are fabricated on a single chip, which improves the performance of circuits in terms of high data transmission speed and power consumption. This requirement of data transmission speed is achieved with the help of high-speed transceivers. In this paper, we present a high-speed asynchronous wave-pipelined serializer and deserializer (SerDes) transceiver implemented using current-mode logic (CML). This asynchronous transceiver circuit does not require a clock and therefore it saves large amount of power which is consumed in the phase locked loop (PLL) and frequency synthesizer circuits. Further, the proposed design is built using CML which saves more power. CML circuit operates at relatively higher speed as compared to CMOS circuits which helps the circuit to operate at higher data rate. Compared to conventional CML latch, a novel CML latch is proposed in our design to increase the speed. The circuit is implemented in standard CMOS 65-nm technology. The total power consumed by the serializer and deserializer is 9.32 mW, which is very less as compared to published related works. The proposed asynchronous SerDes transceiver operates at 18.1-Gbps data transmission rate with low power dissipation. [ABSTRACT FROM AUTHOR]

An energy-efficient (1.02 pJ/b) and high-speed (20.83 Gb/s/wire, 417 Gb/s/mm) link for ultra-short reach (USR) applications (up to 6-dB channel loss at the Nyquist frequency of 12.5 GHz) is presented. Correlated non-return to zero (CNRZ) signaling with low sensitivity to inter-symbol interference (ISI) has been developed to improve the link budget. In addition to high pin efficiency (5b6w: 5 bits over 6 wires), the proposed signaling method provides very good resistance against common-mode and crosstalk noise sources, allowing for dense routing. A very wide-band (1.3 GHz) jitter tracking mechanism has been employed to reduce the sensitivity of the system to random and deterministic jitter and relax design constraints on transmitter. A slicer with low kick-back noise and a circuit topology well matched to the continuous-time linear equalizer (CTLE) has been designed to provide both high input sensitivity and Process, supply Voltage, and Temperature (PVT) variations tolerance. The link operates with more than 22-ps (42.5% UI) eye opening at BER = 1E-15. Calibration loops are running in background for quadrature mismatch error correction, clock and data alignment (CDA), and offset removal. [ABSTRACT FROM AUTHOR]

This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed and routed digital signal processor (DSP) following a 10-bit time-interleaved pipelined successive-approximation register analog-to-digital converter (TI-PISAR ADC). The prototype RX chip implemented in a 14-nm FinFET process demonstrates a lane data rate of 56 Gb/s dissipating 161 mW including the ADC and the DSP power. The energy efficiency of 1.2 pJ/b for the DSP and 2.9 pJ/b for the entire RX was achieved with the data-rate of 56 Gb/s for communicating over channels exhibiting up to 28-dB loss at 14 GHz with a bit-error-rate (BER) better than 2e-4. [ABSTRACT FROM AUTHOR]

Crosstalk noise on the printed circuit board is usually decreased by adding shielding ground (GND). In the trace routing area, the shielding vias are added to isolate the coupling between different traces. In the ball gate array (BGA) and pin field area, assigning more GND pins has demonstrated the effectiveness of crosstalk reduction between signals. However, such design decreases the signal to ground (S:G) ratio dramatically, herein, it is not suitable for applications that require high signal pin density. Unlike the treatment in the conventional methodology, in this paper, the differential crosstalk is mitigated by using the principle of symmetry on two adjacent differential signal pairs in the BGA and pin field regions. New full pin map patterns are proposed and compared with the conventional full pin map patterns. Without sacrificing the S:G ratio, the proposed maps prove the superiority in mitigating both differential far-end and near-end integrated crosstalk noise. To maintain the low crosstalk level in the entire link path, guidance of differential trace routing is provided and demonstrated in the details. All models in this paper satisfy SerDes channel designing and manufacturing requirements. [ABSTRACT FROM AUTHOR]

This paper presents a reconfigurable 56 GS/s transmitter (TX) that operates up to 112 Gb/s with four-level pulse-amplitude modulation (PAM-4) and at 56 Gb/s with non-return-to-zero (NRZ) modulation scheme. Fabricated in the 10-nm FinFET technology, the TX incorporates a four-way interleaved quarter-rate architecture with a three-tap feed-forward equalizer (FFE). Key features of the TX include a 1-UI pulse-generator-based 4:1 serializer combined with a current-mode logic (CML) driver, low-power data-serializing paths, an output pad-network using a multi-segment $\pi $ -coil for bandwidth co-optimization together with ESD diodes, sub-80-fs resolution duty-cycle detector/corrector (DCD/DCC) and quadrature-error detector/corrector (QED/QEC) circuits, and a hybrid LC-phase-locked loop (PLL) with quadrature clock distribution circuits. The TX operating at 112 Gb/s in PAM-4 modulation consumes 232 mW from 1- and 1.5-V supplies, achieving an 2.07 pJ/b energy efficiency. The TX front end occupies an area of 0.0302 mm2. [ABSTRACT FROM AUTHOR]