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This work presents a comprehensive review on radiation hardening techniques aimed at enhancing the resilience of VLSI circuits against soft errors. The study covers a wide approaches for both technological and design-based strategies. Process hardening, shielding, guard rings, silicon on insulator, enclosed layout transistor, masking and transistor sizing are explored to mitigate the impact of radiation-induced errors on VLSI circuit behavior. Furthermore, the paper delves into more advanced methodologies, including TMR, error correction codes, logic duplication, and the integration of guard cells. These techniques offer varying levels of protection against soft errors. The review critically examines the strengths, limitations, and trade-offs associated with each approach, highlighting their suitability for radiation environments. The primary objective of this research is to provide a comprehensive overview of the radiation hardening techniques, which facilitate to understand principles of practical implementations. This review work offers value for VLSI circuit designers and researchers who intend to make electronic systems more reliable in the presence of radiation-induced soft errors with technological and design-oriented approaches. To highlight understanding, we have ended most of the sections and subsections with questions. These questions can help researchers explore related research directions. [ABSTRACT FROM AUTHOR]

Miniaturized electronic devices are essential to improve the performance, reduce the weight and volume, and improve reliability of electronic packages in a spacecraft. With technology scaling, a prime reliability challenge for CMOS devices used in spacecrafts is the occurrence of soft errors due to the propagation of SETs in the space radiation environment. ASICs undergo stringent quality tests to ensure reliable operation of the spacecraft during its mission life. In general, SEE tolerance qualification tests estimate the heavy ion radiation tolerance of CMOS devices for space application. A new SEE test methodology using available scan structure in digital ASICs is proposed. Here, different patterns are loaded in the scan chain which helps to differentiate between SET and SEU soft errors, and test data analysis identifies the SEU fault location. Two different ASIC designs realized in 180 nm CMOS technology are tested in this methodology and detection of SET prone cell is also illustrated. [ABSTRACT FROM AUTHOR]

In this paper, the temperature dependence of single event upset (SEU) cross-section in 28 nm embedded Static Random Access Memory (SRAM) of System in Package (SiP) was investigated. An atmospheric neutron beam with an energy range of MeV~GeV was utilized. The SEU cross-section increased by 39.8% when the temperature increased from 296 K to 382 K. Further Technology Computer Aided Design (TCAD) simulation results show that the temperature has a weak impact on the peak pulse current, which is mainly caused by the change of bipolar amplification effect with temperature. As the temperature increases, the critical charge of the device decreases by about 4.8%. The impact of temperature on the SEU cross-section is determined competitively by the peak pulse current and the critical charge. The impact of temperature on critical charge is expected to become more severe as the feature size is further advanced. [ABSTRACT FROM AUTHOR]

Single Event Upsets (SEUs) are most likely to cause bit flips within the trained parameters of a convolutional neural network (CNN). Therefore, it is crucial to analyze and implement hardening techniques to enhance their reliability under radiation. In this paper, random fault injections into the weights of LeNet-5 were carried out in order to evaluate and propose strategies to improve the reliability of a CNN. According to the results of an SEU fault injection, the accuracy of the CNN can be classified into the following three categories: benign conditions, poor conditions, and critical conditions. Two efficient methods for mitigating weight-related SEUs are proposed, as follows: weight limiting and Triple Modular Redundancy (TMR) for the critical bit of the critical layer. The hardening results show that when the number of SEU faults is small, the weight limiting almost completely eliminates the critical and poor conditions of LeNet-5's accuracy. Additionally, even when the number of SEU faults is large enough, combining the weight limiting and TMR methods for the critical bit of the critical layer can retain the occurrence rate of benign conditions at 98%, saving 99.3% of the hardware resources compared to the Full-TMR hardening method. [ABSTRACT FROM AUTHOR]

This work explains that the Coulomb elastic process on the nucleus is a major source of single-event effects (SEE) for protons within the energy range of 1–10 MeV. The infinite range of Coulomb interactions implies an exceptionally high recoil probability. This research seeks to extend the investigations under which the elastic process becomes significant in the energy deposition process by providing a simplified methodology to evaluate the elastic contribution impact on the reliability of electronics. The goal is to derive a method to provide a simple way to calculate and predict the SEE cross-section. At very low energy, we observe a significant increase in the proton differential cross-section. The use of a direct Monte Carlo approach would mainly trigger low energy recoiling ions, and a very long calculation time would be necessary to observe the tail of the spectrum. In this sense, this work provides a simple methodology to calculate the SEE cross-section. The single-event upset (SEU) cross-section results demonstrate a good agreement with the experimental data in terms of shape and order of magnitude for different technological nodes.

FPGAs are currently being used in many applications due to their flexibility and re-programmability. Some of these applications operate in harsh environments. One such environment is space. Focusing on space applications, these FPGAs are subjected to soft and hard faults. For newer technology nodes, in addition to the harsh space environment, these errors are more severe. This paper investigates several fault-tolerant architectures to mitigate Single Event Upsets (SEUs), Double Event Upsets (DEUs), Triple Event Upsets (TEUs) as well as hard faults. Conventionally, for TEUs, seven copies of a module are required (7MR). Therefore, a modified 7MR architecture is studied along with two other architectures with six redundant modules: a modified 6MR architecture and a modified Triple Duplex architecture. Using Continuous Time Markov Chains (CTMCs), it is proven that, in many of the cases studied in this article, the modified Triple Duplex architecture has a higher reliability than the modified 7MR architecture. This is a counter-intuitive result. It is also proven that the modified 6MR architecture always has a lower reliability than the modified Triple Duplex architecture even though they both require six redundant modules. The ratio between the relative rates of SEUs, DEUs and TEUs plays an important role in determining the most reliable architecture. Furthermore, the Xilinx Vivado tool with the Kintex7, 7k410tfbg676 device is used to implement the modified 7MR and modified Triple Duplex voters to estimate the area and power consumed by these techniques.

This work explains that the Coulomb elastic process on the nucleus is a major source of single-event effects (SEE) for protons within the energy range of 1–10 MeV. The infinite range of Coulomb interactions implies an exceptionally high recoil probability. This research seeks to extend the investigations under which the elastic process becomes significant in the energy deposition process by providing a simplified methodology to evaluate the elastic contribution impact on the reliability of electronics. The goal is to derive a method to provide a simple way to calculate and predict the SEE cross-section. At very low energy, we observe a significant increase in the proton differential cross-section. The use of a direct Monte Carlo approach would mainly trigger low energy recoiling ions, and a very long calculation time would be necessary to observe the tail of the spectrum. In this sense, this work provides a simple methodology to calculate the SEE cross-section. The single-event upset (SEU) cross-section results demonstrate a good agreement with the experimental data in terms of shape and order of magnitude for different technological nodes. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper presents the development and implementation of a software error mitigation technique with the aim of protecting functions to be used in space missions. The Preemptive Control Signature technique is analyzed to mitigate Single Event Upset type errors on the ARMv7E-M architecture and thus be able to extend the availability time of spatial devices by increasing tolerance to such errors. Implemented technique detected 79.5% of the errors.

This paper presents an inventive and extremely dependable radiation-hardened by-design (RHBD) 12T SRAM Cell with enhanced writing capability (RHWC-12T) for a space radiation environment. The Proposed RHWC-12T SRAM is designed on Cadence Virtuoso with quad-storage nodes and simulated in 45-nm CMOS technology with the supply voltage of 1.1 V and 27∘C operating temperature. The proposed cell is tolerant to both 0 to 1 and 1 to 0 SEUs (Single event upsets). Also, it provides better speed and stability compared to the other considered SRAM cells such as 6T, 10T Dohar, Quatro, We-Quatro, QUCCE-12T, and NQuatro. According to simulation findings, the proposed SRAM cell provides 1.053× better writing stability than the 10T Dohar SRAM cell. In addition, the write access time improves by 3.56× with 1.36× area overhead than 10T Dohar SRAM cell.

Summary: Static random‐access memory (SRAM) is a cornerstone in modern microprocessors architecture, as it has high power consumption, large area, and high complexity. Also, the stability of the data in the SRAM against the noise and the performance under the radian exposure are main concern issues. To overcome these limitations in the quest for higher information density by memory element, the ternary logic system has been investigated, showing promising potential compared with the conventional binary base. Moreover, carbon nanotube field effect transistor (CNTFET) is a new alternative device with proper features like low power consumption and threshold voltage dependency on diameter. This paper proposes a new design for ternary SRAM using CNTFET and its evaluation by comparing it against two other designs in many aspects. Moreover, we investigated the static noise margin for the three designs to discuss their stability. Furthermore, we studied the reliability of the designs by evaluating the soft errors effect. [ABSTRACT FROM AUTHOR]

In this study the authors conducted an evaluation of energy management with the aim of identifying energy consumption used for production process activities in the pharmaceutical industry. Based on data on energy use in the productivity process, the Energy Intensity (EI) value ranges from 0.020-0.695 GJ/kg. From these IE values, in each productivity process the average IE value can be used as a reference as an energy conservation limit value of 0.125 GJ/kg. From the description of the pattern of total energy consumption, it can be seen that the use of electrical energy tends to be greater, namely around 66.37% compared to the consumption of CNG and diesel which only consume 31.80% and 1.83%. The total energy use for electricity is an average of 1,105.56 MWh/month, CNG fuel is 1,895.54 MMBTU/month and diesel is 3.04 liters/month. In terms of equipment systems, the largest electricity consumption is borne by the HVAC system which consumes around 55.56% of the total electrical energy. From the description of the distribution of electrical energy use, it can be said that the HVAC system is SEU (Significant Energy Use). Based on actual conditions, it shows that the actual COP value obtained is 2.49-2.98 with a design deviation of around 1.24%-27.74% and an EER value of 1.18-1.41 kW/TR with a design deviation value of around 1.17%- 38.22%. COP and EER values can still be increased so that performance is more optimal. [ABSTRACT FROM AUTHOR]

All electronic devices when used in a radiation environment undergo significant changes in their electrical properties. It is interesting to explore the effects of radiation, not only on conventional MOSFET devices but also on novel devices like FinFET, Tunneling Field Effect Transistor (TFET), and Junctionless Field Effect Transistor (JLFET). This study presents a systematic review of radiation studies on TFET and JLFET-based devices/circuits. TFET and JLFET have gained popularity in recent days due to their wide use in ultra-scaled designs than conventional CMOS. The effect of radiation on a divergent range of TFET and JLFET devices and circuits is explored. The variations in DC characteristics and electrical parameters under the influence of radiation strikes are analyzed in detail. The radiation effects like Total Ionizing Dose (TID), and Single Event Upset (SEU) are noted for these devices/circuits. The radiation study on different devices shows that these devices are sensitive to Single Event Effect (SEE), steeper Subthreshold Swing (SS), increase in Electron Hole Pair (EHP) production, increase in drain current (ID), and increase in collected charge (QC), decrease in bipolar gain and trans-conductance. [ABSTRACT FROM AUTHOR]

Evolvable hardware-based fault-tolerant hardware design is an efficient approach to self-adaptability. It is an essential feature to mitigate errors on the fly. But there are two issues while designing an adder using the evolutionary hardware (EHW) approach: scalability issues in circuit representation and a low error recovery speed due to many evolutions. To avoid scalability issues, we designed an optimized virtual reconfiguration circuit (VRC) for adder. In this paper, we introduce the chromosome reconstruction algorithm for evolving the circuit to recover faults in an adder circuit at a faster speed. The proposed self-healing adder design is implemented on a single FPGA using an intrinsic approach. The complete hardware is designed on a Proasic A3PE3000 FPGA. Compared to existing work, the proposed work's resource utilization is optimal. [ABSTRACT FROM AUTHOR]

Copyright of Cuadernos de Historia Contemporanea is the property of Universidad Complutense de Madrid and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The aerospace environment contains extremely energetic particles that trigger single-event transients (SET), leading to single-event upsets (SEU) in the memory cell. An efficient SRAM cell must be designed to tolerate soft error to withstand the extreme environment. This paper proposes a highly efficient radiation hardened-by-design 12T P-Quatro SRAM cell based on a polarity upset mechanism. The proposed cell has better writability, and WSNM is 1.08 × higher than its counterpart We-Quatro SRAM cell. The read access time of the proposed SRAM cell is 0.96 × , 0.91 × , 0.99 × , 0.98 × smaller than 6T, Quatro, We-Quatro, and NQuatro SRAM cells, and 1.01 × higher than RHD12T cell, and the write delay of the proposed SRAM is 0.93 × , 0.46 × , 0.72 × , 0.41 × , 0.47 × , less than that of 6T, Quatro, We-Quatro, RHD12T, and NQuatro respectively. 2000 Monte Carlo simulation for power dissipation and upset margin reveals that the process variation has less impact on the proposed SRAM and 1.64 × better tolerance against logic flipping. Further, for the P-Quatro, the critical charge is 41.51 fC and is 2.05 × , 1.75 × , 1.93 × , and 1.48 × greater than Quatro, We-Quatro, RHD12T, and NQuatro memory cells. We conducted an assessment using an electrical quality matrix (EQM) that takes into account all performance parameters. The findings reveal that the EQM of the proposed cell surpasses that of the 6T, Quatro, We-Quatro, RHD12T, and NQuatro SRAM cells by factors of 0.82 × , 0.35 × , 0.49 × , 0.71 × , and 0.21 × , respectively. This indicates that the proposed cell demonstrates superior electrical quality across various metrics compared to the other SRAM cell designs evaluated. • A highly efficient radiation hardened-by-design 12T P-Quatro SRAM cell based on a polarity upset mechanism. • Using NMOS transistors instead of PMOS helps reduce charge sharing in the circuit, improving critical charge and reducing soft error upset probability. • The electrical quality matrix (EQM) of the proposed cell surpasses that of the 6T, Quatro, WeQuatro, RHD12T, and NQuatro SRAM cells. [ABSTRACT FROM AUTHOR]

With the successful development of information technology, particularly in big data and neural network scopes, the appetency for denser memory compositions has exponentially outreached. Accordingly, multi-valued logic has extensively been explored as a promising solution for data storage density enhancement and interconnect complexness declining, integrating with emerging nonvolatile nanodevices. This paper presents a reliable nonvolatile 3-transistor 1-RRAM (3T1R) ternary memory cell and its compact array architecture fulfilled on hybrid RRAM/FinFET logic, in which the cell layout can be densely plugged into the memory array architecture. Comprehensive post-layout simulations based on 7nm FinFET technology have been conducted to assess the proposed design’s functionality, performance, and reliability. Our proposed ternary 3T1R cell has exceptional immunization confronting radiations availing the RRAM radiation immunity and innovative circuit structure. Meanwhile, the RRAM’s engrossing nonvolatile nature induces no static power dissipation in the hold state, certified for low-power applications. Moreover, Monte-Carlo simulation results demonstrate the roughly 20% functional failure of the 1T1R cell’s ternary implementation facing process-voltage-temperature (PVT) variations. However, the proposed design operates robustly in the presence of PVT variations with no functional failure while offering lower delay and energy consumption. Meanwhile, it is also well-designed for addressing the Fin quantization impact of FinFET.

Single event upsets (SEU) are the transient errors that occur during the operation of the circuit. High radiation in the space environment and its invasion of the nanoelectronics can result in a bit-flip in the combinational circuits and may cause a stuck-at fault in the sequential circuit. Faults are unacceptable for any application, especially SEU in the control path, which is crucial and imperative since it can lead to functional or even mission failure. As a result, this paper proposes a bio-inspired technique based on a modified heuristic-guided genetic algorithm to mitigate error at the Finite State Machine (FSM), which is the controller's behavior model. The proposed architecture performs an optimized functional level evolution of the FSM intrinsically on ProAsic3e FPGA boards without the help of System-on-Chip (SoC). Due to this, the delay caused by extrinsic and hybrid evolution has been reduced. The proposed heuristic-guided genetic algorithm recovers the fault in the control circuit with less convergence time when compared to the standard genetic algorithm. The resource utilization of the proposed evolvable hardware system has reduced costs compared to traditional functional evolution. [ABSTRACT FROM AUTHOR]

This article is a survey of models used for the calculation of proton single-event upset (SEU) cross-sections from heavy-ion data. Models are evaluated using data in the published literature. The best predictions were given by the analytic models with no free parameters. However, in many cases, the models underpredict the measured cross-section, and a lack of precision may prevent a good prediction on a given device. Additionally, the data used to derive the models has not changed significantly over the last 30 years. [ABSTRACT FROM AUTHOR]

• Reliability aspect of the SFP-MISHEMT under the linearity and SEU environment have been demonstrated. • Temperature related degradation has also been explored and the results have been investigated with varying device parameters. • Compared to conventional MISHEMT, SFP-MISHEMT shows better linearity in terms of higher VIP 2 , IIP 3 and lower intermodulation distortion. • The influence of process variability has also been studied. • Improved reliability in terms of the lesser SEU generated effects has been observed from the SFP-MISHEMT. In this work, the reliability of Slant Field Plate SFP-MISHEMT has been discussed using linearity and Single Event Upset parameters for millimeter wave (mmW) applications in outer space environment. The influence of process variability on the RF and linearity parameters of SFP-MISHEMT like g m ' and g m ", higher VIP 2 , IIP 3 and IMD 3 has also been explored. For analyzing the SEU behavior, three different positions of the ion strike have been used and the investigation has been conducted with varying energy and device parameters like temperature. The impact of the gate to drain length (L gd) and oxide permittivity and gate length (varied from 60 nm to 210 nm keeping the length of the SFP constant as 20 nm (on both side)) on the device sensitivity has also been explored. Improved reliability in terms of the lesser SEU generated effects has also been observed from the SFP-MISHEMT in contrast with C-MISHEMT. [ABSTRACT FROM AUTHOR]

Single event upset (SEU) refers to the change in the state of a digital circuit caused by a single, energetic particle passing through the sensitive area of semiconductor components. In the space environment, cosmic rays and high-energy particles may lead to SEUs, which can cause failures of routing functions, such as forwarding errors, in satellite networks. This paper focuses on the impact of SEUs on satellite networks from the perspective of distributed routing. The influence of SEUs on a single satellite can easily spread to the entire satellite network through distributed routing, which can influence the reliability of the satellite network. We propose a framework for the reliability analysis of satellite networks under the impact of SEUs. According to the influence of SEUs on the execution of routing programs in different routing phases, we present the error propagation model of satellite networks for understanding SEUs in satellite network routing. We found that all the influences on program execution ultimately converge on data forwarding and can be reflected in the proposed path topology graph. Therefore, we propose an algorithm that can evaluate the impact of SEUs on satellite networks by analyzing the path topology graphs in both normal and SEU scenarios. The feasibility and effectiveness of the proposed method is demonstrated by experiments. The proposed method could provide a new perspective and theoretical basis for research on secure routing mechanisms and program/instruction reinforcement. [ABSTRACT FROM AUTHOR]

Soft errors induced by Single Event Transient (SET) or Single Event Upset (SEU) are a great threat to integrated circuits. To reduce the error rate and improve the reliability of the circuits, we proposed a radiation hardened flip-flop in this paper, namely, Soft Error Detection and Recovery flip-flop (SEDR-FF). Error detection is based on delayed sampling and redundant storage by a redundant latch. A pulsed clock is adopted to control the redundant latch to reduce the hold time constraint of the latch. To generate the pulsed clock, two efficient delay elements are presented in this paper. Error recovery is accomplished by reloading the previous data stored in a history latch. Transistor-level simulations and timing-annotated gate-level simulations under 65 nm technology show that the proposed flip-flop can efficiently detect and correct the soft errors caused by SET or SEU. It has low overhead of setup time, and is suitable for high-performance designs. In addition, compared with other radiation hardened cells, the proposed flip-flop has moderate power and area overhead, and has lower area cost for fixing hold time violations in circuits designs. [ABSTRACT FROM AUTHOR]

In this article, a class of machine-learning techniques that implement model-averaging are used for the calculation of proton single-event upset (SEU) cross-sections from heavy-ion data. Calculations are checked using data on proton and heavy-ion cross-sections from the published literature. These techniques improve the accuracy of the calculation. Model averaging techniques were predicted the proton cross-section within an order of magnitude in better than 75% of the test cases. However, these techniques did little to improve the precision of the model predictions, and typically had an error bar of about 300%. [ABSTRACT FROM AUTHOR]

In this work, the impact of shallow trench isolation (STI) and dual stress liner (DSL) -induced stresses on soft error performance of 30-nm gate length Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET)-based 6T-SRAM cells is studied using process and device simulations. Under nine different stress combinations, i.e., nine different SRAMs, our simulation results show that the stresses introduced from STI and DSL enhance the soft error performance of the cells significantly. [ABSTRACT FROM AUTHOR]

The Micro-Programmed Control Unit (MPCU) offers an alternative to conventional hardwired control circuits by employing a control store for transmitting control signals through stored control bits. Traditionally, Hamming codes are used for Single-Event Upset (SEU) protection in memory components. However, these Error Control Codes (ECC) encounter challenges, such as inconsistent code rates and limited adaptability for Multiple Bit Upsets (MBU). To address MBU protection, ECC codes with soft decoding logic are commonly utilized, leading to increased hardware complexity. This paper introduces a lightweight encoding and hard-decoding logic capable of detecting and correcting up to n 2 ∗ upsets, achieving a code rate of ≈ 0.37. Through evaluations against both traditional and recent ECC methods, the proposed approach demonstrates enhanced fault correction capabilities compared to Hamming codes. Furthermore, it maintains a consistent code rate, incurs lower area overhead, and exhibits less hardware complexity than MBU codes by employing hard decoding logic. The suggested methodology effectively mitigates both MBU and SEUs in control stores, providing reduced delay and making it well-suited for ensuring reliability in high-speed memory applications like MPCUs. • A hard decision-ECC scheme for SEU and MBU mitigation. • A lightweight encoder and decoder logic for Microprogrammed control unit. • A consistent code rate ECC for any control word of length n. • Minimum decoder circuit path delay to reduce the latency. • Marginal miscorrection rate for absolute fault mitigation. [ABSTRACT FROM AUTHOR]

Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities such as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them, and test escapes may occur. These undetected faults, associated with weak resistive defects, may affect the FinFET-based SRAM reliability during its lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed allowing the evaluation of the ionizing particle's impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects can positively or negatively influence the cell reliability against SEUs caused by ionizing particles. [ABSTRACT FROM AUTHOR]

A triple modular redundancy SRAM was designed as the embedded high-speed memory for a radiation-tolerant ARM processor with ST Microelectronics 28-nm FDSOI technology. The single event upset (SEU) cross-section of the SRAM was tested by using heavy ions with the linear energy transfer of 15.0 meV.cm2.mg−1 in both non-TMR and TMR modes with different accumulated fluence. The SRAM cell was also simulated by using Cogenda TCAD simulation suite and the cross section was calculated by using analytic method. The results showed the cross-section is around 2E-10 cm2/bit in non-TMR mode, and in TMR mode it varied from one to several orders lower than the non-TMR mode according to the specific accumulated fluence. As a scrubbing circuit was designed to reduce the accumulated number of SEUs in the SRAM, the Failure In Time (FIT) rate at sea level in New York City could be as low as 8E-11, which is robust enough for the whole circuit. [ABSTRACT FROM AUTHOR]

Copyright of Tropelías: Revista de Teoría de la Literatura y Literatura Comparada is the property of Prensas Universitarias de Zaragoza and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The Embedded system design is characterized by its daily complexity. It integrates a hardware and software parts together on a common platform. These parts may be defective by a spurious signal, subsequently found to be two types of errors. The software and hardware errors can attack the embedded system. In this paper an exhaustive analysis of the effects of Single Event Upset into the Static Random Access Memory occupied area of Aeroflex Gaisler LEON3 processor is presented. It is a soft core pipeline processor that is part of the GRLIB IP library based on Scalable Processor Architecture, SPARC V8,implemented in Virtex-5 FPGA. A new software methodology allowing fault injection is explored and illustrated in order to classify the defective behaviours while executing several benchmarks. This investigation is done by an exhaustive fault injection campaign (More than 200000 transient faults) into SRAM memory of LEON3 considered as a processor. The proposed method makes error rate predictions more accurate compared to other techniques.

In radiation tests on SRAMs or field-programmable gate arrays (FPGAs), two or more independent bitflips can be misled with a multiple event if they accidentally occur in neighbor cells. In the past, different tests, such as the “birthday statistics,” have been proposed to estimate the accuracy of the experimental results. In this article, simple formulas are proposed to determine the expected number of false 2- and 3-bit multiple cell upsets (MCUs) from the number of bitflips, memory size, and the method used to search multiple events. These expressions are validated using the Monte Carlo simulations and experimental data, and a technique is proposed to refine the experimental data and thus partially removing possible false events. Finally, it is demonstrated that there is a physical limit to determine the cross section of memories with arbitrary accuracy from a single experiment. [ABSTRACT FROM AUTHOR]

When a single event upset occurred in the data flow - driven computation channel，it produces erro-neous results or even the computational channel will not function properly. For this reason，this study proposed a dual -mode redundant fault - tolerant scheme based on address rewinding technology，which used double computing channel comparison to detect whether the error occurs. The address rewinding technique was used to restore the address information and drive the original data to be recalculated. A specific optimized rewind on the correlation data stream calculations was also performed in the study. Based on the data stream driven operator，the scheme was implemented .The experimental results showed that the scheme achieved a reliability rate of over 99%，the area cost was only 76% of the three - mode redundancy，and the time overhead was up to 50% compared witli the dual - mode redundancy， indicating the scheme successfully achieved a balance bet"ween area and time consumption. [ABSTRACT FROM AUTHOR]

This article proposes a method using electron and proton Single Event Upset sensitivities of a device to deduce all simulation parameters related to an RPP approach. It is shown that for 45-nm double data rate (DDR) memory, the RPP approach is still relevant and the crossing of proton and electron data makes it possible to constrain and properly define the associated parameters. Heavy ion prediction is also presented. [ABSTRACT FROM AUTHOR]

Selenium (Se) is an essential trace element for many organisms, which is required in the biosynthesis of proteins with selenocysteine, tRNAs with selenouridine, and certain enzymes with Se as a cofactor. Recent large-scale metagenomics projects provide a unique opportunity for studying the global trends of Se utilization in marine environments. Here, we analyzed samples from different marine microbial communities, revealed by the Tara Oceans project, to characterize the Se utilization traits. We found that the selenophosphate synthetase gene, which defines the overall Se utilization, and Se utilization traits are present in all samples. Regions with samples rich and poor in Se utilization traits were categorized. From the analysis of environmental factors, the mesopelagic zone and high temperature (> 15°C) of water are favorable, while geographical location has little influence on Se utilization. All Se utilization traits showed a relatively independent occurrence. The taxonomic classification of Se traits shows that most of the sequences corresponding to Se utilization traits belong to the phylum Proteobacteria. Overall, our study provides useful insights into the general features of Se utilization in ocean samples and may help to understand the evolutionary dynamics of Se utilization in different marine environments. [ABSTRACT FROM AUTHOR]