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60 results on '"SIRIBURANON, T"'

1. A 50.1Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay with Calibration of LO Feed-Through and I/Q Imbalance

Author

Pang, Jian, Jian, Pang, Maki, Shotaro, Kawai, Seitaro, Nagashima, Noriaki, Seo, Yuuki, Dome, Masato, Katou, Hisashi, Katsuragi, Makihiko, Kimura, Kento, Kondo, Satoshi, Terashima, Yuki, Liu, Hanli, SIRIBURANON, T, Siriburanon, Teerachot, THARAYILNA, ARAVIND, Aravind, Tn, NURUL, FAJRI, Fajri, Nurul, Kaneko, Tohru, Yoshioka, Toru, Liu, Bangan, Wang, Yun, Wu, Rui, Li, Ning, Tokgoz, KorkutKaan, Tokgoz, Korkut Kaan, Nohara (Miyahara), Masaya, Shirane, Atsushi, and Okada, Kenichi

Published
2019

5. A Low-Power Low-Noise mm-Wave Sub-Sampling PLL using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE802.11ad

Author

SIRIBURANON, T, Siriburanon, Teerachot, Kondo, Satoshi, Katsuragi, Makihiko, Liu, Hanli, Kimura, Kento, Deng, Wei, Okada, Kenichi, and Matsuzawa, Akira

Subjects
Frequency synthesizer, Physics, business.industry, Transconductance, 020208 electrical & electronic engineering, Electrical engineering, dBc, 020206 networking & telecommunications, 02 engineering and technology, Topology, Injection locking, Frequency divider, Phase-locked loop, CMOS, Phase noise, 0202 electrical engineering, electronic engineering, information engineering, Electrical and Electronic Engineering, business
Abstract

This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique in a QILO helps boost negative transconductance $({{-g}}_{m})$ of the 60 GHz QILO which allows the use of larger inductance for power reduction. Implemented in 65 nm CMOS, it can cover required channels from 58.32 to 64.80 GHz with quadrature outputs. It consumes 24.2 and 7.8 mW from 20 GHz SS-PLL and QILO, respectively. The proposed synthesizer achieves $-78.5\; \text{dBc/Hz}$ at 100 kHz offset, $-122\text{dBc/Hz}$ at 10 MHz offset, and a figure-of-merit (FoM) of $-236\text{dB}$ .

Published
2016

6. A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit

Author

SIRIBURANON, T, Siriburanon, Teerachot, Deng, Wei, Okada, Kenichi, and Matsuzawa, Akira

Subjects
Voltage-controlled oscillator, Materials science, CMOS, business.industry, Replica, Electronic engineering, Electrical engineering, Constant current, Electrical and Electronic Engineering, Start up, Self adjusting, business, Electronic, Optical and Magnetic Materials
Published
2015

7. A Fully Synthesizable All-digital PLL with Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-resolution Digital Varactor Using Gated Edge Injection Technique

Author

Deng, Wei, Yang, Dongsheng, Ueno, Tomohiro, SIRIBURANON, T, Siriburanon, Teerachot, Kondo, Satoshi, Okada, Kenichi, and Matsuzawa, Akira

Subjects
Engineering, business.industry, Design flow, Hardware_PERFORMANCEANDRELIABILITY, Power (physics), Phase-locked loop, Injection locking, PLL multibit, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Electrical and Electronic Engineering, business, Varicap, Electronic circuit, Jitter
Abstract

This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power.

Published
2015

9. 64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay

Author

Wu, Rui, Minami, Ryo, Tsukui, Yuuki, Kawai, Seitaro, Seo, Yuuki, Sato, Shinji, Kimura, Kento, Kondo, Satoshi, Ueno, Tomohiro, NURUL, FAJRI, Fajri, Nurul, Maki, Shotaro, Nagashima, Noriaki, Takeuchi, Yasuaki, Yamaguchi, Tatsuya, AHMED, MAGDI MUSA, Musa, Ahmed Magdi Hassan, Tokgoz, KorkutKaan, Tokgoz, Korkut Kaan, SIRIBURANON, T, Siriburanon, Teerachot, Liu, Bangan, Wang, Yun, Pang, Jian, Jian, Pang, Li, Ning, Nohara (Miyahara), Masaya, Okada, Kenichi, and Matsuzawa, Akira

Published
2017

10. Ultra-High-Data-Rate 60-GHz CMOS Transceiver for Future Radio Access Network

Author

Wu, Rui, Minami, Ryo, Tsukui, Yuuki, Kawai, Seitaro, Seo, Yuuki, Sato, Shinji, Kimura, Kento, Kondo, Satoshi, Ueno, Tomohiro, NURUL, FAJRI, Fajri, Nurul, Maki, Shotaro, Nagashima, Noriaki, Takeuchi, Yasuaki, Yamaguchi, Tatsuya, AHMED, MAGDI MUSA, Musa, Ahmed Magdi Hassan, Tokgoz, KorkutKaan, Tokgoz, Korkut Kaan, SIRIBURANON, T, Siriburanon, Teerachot, Liu, Bangan, Wang, Yun, Pang, Jian, Jian, Pang, Li, Ning, Nohara (Miyahara), Masaya, Okada, Kenichi, and Matsuzawa, Akira

Published
2017

14. A Compact, Low Power and Low Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration

Author

AHMED, MAGDI MUSA, Musa, Ahmed Magdi Hassan, Deng, Wei, SIRIBURANON, T, Siriburanon, Teerachot, Miyahara, Masaya, Okada, Kenichi, and Matsuzawa, Akira

Subjects
Engineering, business.industry, Dual loop, Hardware_PERFORMANCEANDRELIABILITY, Feedback loop, Power (physics), Phase-locked loop, Voltage-controlled oscillator, CMOS, Low-power electronics, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Electrical and Electronic Engineering, business, Jitter
Abstract

This paper presents a low-jitter, low-power and a small-area injection-locked all-digital PLL (IL-ADPLL). It consists of a dual-loop and a dual-VCO architecture in which one VCO (Replica) is placed in a TDC-less synthesizable ADFLL to provide continuous tracking of voltage and temperature variations. The other VCO (main) shares the control voltage with the replica VCO but is placed outside the loop and is injection-locked to lower its jitter and accurately set its frequency to the desired one. This approach avoids timing problems in the conventional ILPLL since the injection-locked VCO is placed outside the feedback loop. It also achieves a low power and a small area, due to the absence of a power hungry TDC and an area-consuming loop filter, while tracking any PVT variations. The IL-ADPLL is implemented in a 65 nm CMOS process and measurement results show that it achieves a 0.7ps RMS jitter at 1.2 GHz while having 1.6 mW and 0.97 mW power consumption with and without intermittent operation resulting in an FOM of -243 dB. It also consumes an area of only 0.022 mm2 resulting in the best performance-area trade-off system presented up-to-date.

Published
2014

15. A 20GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60GHz Frequency Synthesizer

Author

SIRIBURANON, T, Siriburanon, Teerachot, Sato, Takahiro, AHMED, MAGDI MUSA, Musa, Ahmed Magdi Hassan, Deng, Wei, Okada, Kenichi, and Matsuzawa, Akira

Subjects
Physics, Frequency synthesizer, Offset (computer science), Impulse sensitivity function, business.industry, Electrical engineering, dBc, Electronic, Optical and Magnetic Materials, Voltage-controlled oscillator, Resonator, Power consumption, Phase noise, Electrical and Electronic Engineering, business
Abstract

This paper presents a 20 GHz push-push VCO realized by a 10 GHz super-harmonic coupled quadrature oscillator for a quadrature 60 GHz frequency synthesizer. The output nodes are peaked by a tunable second harmonic resonator. The proposed VCO is implemented in 65 nm CMOS process. It achieves a tuning range of 3.5 GHz from 16.1 GHz to 19.6 GHz with a phase noise of −106 dBc/Hz at 1 MHz offset. The power consumption of the core oscillators is 10.3 mW and an FoM of −181.3 dBc/Hz is achieved. key words: low phase noise, low power, tail-current modulation, impulse sensitivity function, super-harmonic coupled QVCO, push-push VCO

Published
2013

21. A 42Gb/s 60GHz CMOS Transceiver for IEEE802.11ay

Author

Wu, Rui, Kawai, Seitaro, Seo, Yuuki, NURUL, FAJRI, Fajri, Nurul, Kimura, Kento, Sato, Shinji, Kondo, Satoshi, Ueno, Tomohiro, SIRIBURANON, T, Siriburanon, Teerachot, Maki, Shotaro, Liu, Bangan, Wang, Yun, Nagashima, Noriaki, Miyahara, Masaya, Okada, Kenichi, and Matsuzawa, Akira

Published
2016

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