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The paper presents the noise analysis of a MEMS and ASIC readout integrated circuit (ROIC) constituting the accelerometer developed in the frame of the InnoReh project, aiming at the development of methods for monitoring patients with imbalance disorders. Several experiments were performed at different temperatures and in different configurations: ROIC alone, ROIC with emulated parasitic capacitances, MEMS and ROIC in separate packages, and MEMS and ROIC in a single package. Many noise/interference sources were considered. The results obtained experimentally were compared to the results of theoretical investigations and were within the same order of magnitude, although in practice, the observed noise was always greater than the theoretical estimation. The paper also includes an in-depth analysis to explain these differences. Moreover, it is argued that, in terms of noise, the MEMS sensing element, and not the ROIC, is the quality-limiting factor. [ABSTRACT FROM AUTHOR]

In this paper, a two-stage, single-phase, multilevel dc/ac converter for PV system is proposed. The typical two-stage inverter in PV systems requires a high dc-link voltage, and a step-up dc/dc converter is used. However, a two-stage power conversion requires a high number of power electronic components, resulting in higher cost and lower efficiency. Compared to the similar seven-level inverter, the proposed topology provides three times step-up voltage ratio and a smaller number of circuit components. The introduced topology consists of two stages, the front stage is a step-up dc/dc converter-based switched capacitor circuit. This stage provides high voltage boasting ratio and self-balancing dc-link voltage capacitors capability. Furthermore, a soft switching operation for the power switching devices is implemented using the LC-resonant circuit; thus, peak current amplitude can be regulated, electromagnetic noise and switching losses are significantly decreased. The second stage is a seven-level dc/ac inverter and has the advantages of fewer numbers of semiconductor devices. The operating principles and the modulation scheme of both stages are analyzed and discussed. Simulation and experimental results are provided to prove the effectiveness of the presented topology under different operating conditions. [ABSTRACT FROM AUTHOR]

This paper presents a novel concept of a DC-AC converter that ensures AC voltage modulation on four levels using a single branch and achieves voltage boosting. The proposed boost inverter is based on a single-stage topology and does not use a DC-DC boosting part. Compared with a cascaded boost inverter topology, the proposed converter is bidirectional and allows operation at a lower DC-link voltage, which reduces voltage stress across devices. The inverter topology contains an additional DC capacitor. An adequate voltage level for this capacitor is maintained by a switched-capacitor-based (SC)-based balancing circuit. The balancing process is of low complexity because it only requires the synchronization of the SC branch control signals with the PWM of the inverter. The balancing circuit operates in resonant mode to avoid inrush currents. The main power circuit of the converter does not use diodes, and can be adequate for MOSFET or GaN-based implementations. It can be configured as a single-phase or multiphase system. The results presented in this paper demonstrate the correctness of the converter concept and its modulation, voltage stresses of switches, and balancing process of the auxiliary capacitor. The experimental results confirm the feasibility of this concept and demonstrate the operation and efficiency of the inverter.

Dickson-type dc-dc converters have gained renewed interest in recent years due to their best-in-class volt-amp switch utilization. In addition, 'hybrid' switched-capacitor (HSC) structures increase passive component utilization while avoiding the slow-switching limit (SSL), and yet, most HSC work to date has done little to assess large signal voltage ripple behavior and subsequent passive utilization limits. This work contributes a comprehensive review of contemporary Dickson-type HSC converters before introducing eight fundamental reduced HSC Dickson structures, including three that are proposed here. Analysis allowing characterization of large signal operating points, capacitor sizing regimes, switching schemes, and maximum allowable power throughput is introduced. The analysis for 'split-phase' switching is also presented in detail, without making small ripple approximations. Furthermore, an expression for large ripple flying capacitor energy density utilization is derived, assisting with optimal topology selection and revealing that split-phase operation may be preferable for conversion ratios greater than 6:1. All analysis is verified in simulation, with an additional discrete hardware prototype further validating a complex case of resonant split-phase timing. The analytical results of 17 distinct Dickson variations are recorded, assisting with topology selection and design.

The generation of electricity from renewable sources has made considerable strides in today's industrialized nations. The primary objective of this research is to examine the grid integration of solar systems within permissible total harmonic distortion (THD) limits, with the help of a proposed cascaded feedforward neural network (CFNN) controller fed advanced power conversion devices such as symmetrical hybrid (SH), switched inductor (SL), and switched capacitor (SC) based boost converter and reduced switch cascade multilevel inverter (CMLI). The SH–SL–SC converter for power conversion features a high voltage gain and reduced switch CMLI features minimum number of power electronic switches and low harmonic content in both the voltage and current profiles. When producing a control signal for the recommended SH–SL–SC boost converter, the proposed CFNN-MPPT controller performs better under different weather scenarios where it needs significant data to operate effectively. Consequently, the CFNN-MPPT controller fed SH–SC–SC boost converter-based PV system is integrated into the grid through reduced switch CMLI where it is controlled by proposed CFNN controller. The CMLI can be operated on asynchronous input voltage sources and making it ideal for PV systems when integrated to the grid with improved power quality by reducing total harmonic distortion (THD) to less than 5% at point of common coupling. With reference to the standards outlined in IEEE 1547 and 519, the simulation's outcomes were reviewed. Finally, a symmetric hybrid SL–SC boost converter and modified cascaded nine level inverter have been conceived and produced as a laboratory prototype model and its output waveforms are presented in this article. The proposed intelligent controller fed converter exhibits enhancements in the converter voltage gain and power quality by lowering the THD level at PCC in the grid integration with the PV power systems. [ABSTRACT FROM AUTHOR]

This paper presents an adderless feed-forward incremental Δ Σ (I Δ Σ ) with asynchronous SAR (ASAR) that removes the need for in-column calibration by using global references, eliminates an additional summing amplifier and reduces the conversion time by using a multi-bit ASAR quantizer. The proposed I Δ Σ ADC is designed in 40 nm CMOS technology and is laid out compactly in a 5 μ m × 466 μ m column. According to post-layout simulations, the ADC achieves an input-referred noise of 85 μ V rms , a conversion time of 3.2 μ s (with DCDS) and a power consumption of 230 μ W. This results in a Walden FoM W of 234 fJ/conv.step and a FoM A = FoM W × A ADC of 0.54 fJ · mm 2 /conv.step, which demonstrates the feasibility of using the proposed architecture in CMOS image sensors. [ABSTRACT FROM AUTHOR]

A single-phase bidirectional DC/DC battery charger with a P&O MPPT current control strategy for a standalone energy management system has been integrated with an interleaved switched capacitor DC/AC inverter with an RMS feedback phase-shifted unipolar sinusoidal PWM control strategy. In the published literature, P&O MPPT control is used to drive a boost converter connected in parallel to a battery charger; this modified strategy combines a P&O MPPT algorithm with current control to drive an interleaving buck-boost battery charger. This battery charger circuit is connected in parallel to a closed loop controlled interleaved inverter that feeds the AC home load. MATLAB/Simulink based simulation circuit was developed and used to validate the successful integration of the interleaved battery charger with the global system. To do this, the system is tested with varying input conditions of irradiance and temperature. The system's response to these variable inputs is monitored and analysed. The simulation results show the proposed method is effective for standalone battery-based PV systems. The system provides a more efficient and faster response compared with both an interleaved and non-interleaved voltage-controlled battery charger circuit that is also integrated with the global system. This battery charger control strategy is also shown to protect the battery from over-charging as well as discharging below 25%, which can improve and protect the long-term battery performance. Compared with novel industry approaches, the proposed system is simpler by nature due to the reduced number of conversions and therefore a reduced number of components which provides economic advantages. [ABSTRACT FROM AUTHOR]

Power factor plays an important role in electrical industries. Low power factor results in loss of power and poor handling capacity. This factor can be overcome by using capacitors in parallel to the load. Since capacitor draws a leading while inductor draws a lagging current, hence by adjusting capacitor banks parallel to the load, it will level the power factor in the line. Earlier, the process of power factor improvement was done through manual connection of capacitor bank. Later a power factor corrector named the automated power factor corrector (APFC) was proposed. It uses a switched capacitor circuit to improve power factor. In this research, the power factor value from the load is measured and it also includes the installation of APFC unit using a PI controller. The design of this auto-adjustable power factor correction scheme is to ensure that the grid power system always operates under the specified power factor. Actual work of APFC is that it selects the capacitor bank for power factor improvement. The capacitor bank block will choose automatically to further improve the power factor. This process goes on until the required power factor is obtained. Later on, this will automatically turn off the connection between the capacitor bank and the circuit. Furthermore, power saving with power factor after improvement is also discussed in the paper. Here APFC plays a key role in order to decrease the time taken to correct the power factor, which is ultimately beneficial to increase the efficiency of the motors and all inductive loads.

Single-phase switched-capacitor multilevel inverters are an excellent alternative for low-power applications as they provide high voltage gain. However, their control and modulation are not simple due to the particularity of these topologies. Finite Control-Set Model Predictive Control (FCS-MPC) has therefore emerged as an attractive control alternative for these inverters. This article seeks to establish guidelines for the implementation of FCS-MPC in this type of inverter. To that end, FCS-MPC is implemented in two topologies that have previously been described in the literature as well as in a new topology. The results establish excellent methodological guidelines for applying FCS-MPC in this family of inverters, that achieve high dynamic responses.

There is an increasing need for more efficient power conversion from 48 Vdc to point-of-load (PoL) applications in datacenters. This work presents a new hybrid converter with Multi-Level Binary (MLB) voltages on the flying capacitors that is well-suited for PoL applications with very high conversion ratios. The proposed MLB-PoL converter can be viewed as an 8-to-1 multi-phase doubler switched-capacitor (SC) converter merged with a two-phase interleaved buck converter. Compared to other two-phase hybrid SC topologies, multi-phase operation can help achieve higher conversion ratio in the SC stage with an equal or fewer number of components, and thus reduce the switch andinductor stress of the following buck stage. In addition, the output inductors in the proposed topology benefit from a frequency multiplication effect similar to that of the flying capacitor multilevel (FCML) converter. This can help further reduce the inductor size without increasing the switching frequency. A 48 V to 2.5-1.0 V converter prototype with 65 A output current was built and tested. At 48 V to 2 V, the prototype achieved 95.1% peak efficiency (94.3% including gate drive loss) and 395 W/in3 power density.

This study proposes a novel bidirectional-switched-capacitor-based interleaved converter. In view of the shortcomings of the two well-known unidirectional-switched-capacitor-based interleaved converters, this study improves such converters through combining the novel structure of a switched capacitor circuit. The first effort was to overcome the drawback of the Cockcroft–Walton-based interleaved converter, whose circuit impedance and ripple cause a serious output voltage drop. The second was to solve the Dickson-based interleaved converter with its capacitors subjected to high-voltage stress. The third was to relax the unidirectional boost function of the Cockcroft–Walton- or Dickson-based interleaved converter. This study avoided not only high-circuit impedance and ripple, as in the case of the Cockcroft–Walton converter, but also it had lower component stress than the Dickson converter. In addition, this study redesigned the unidirectional boost function of the Cockcroft–Walton- or Dickson-based interleaved converter, such that the switch-capacitor-based interleaved converters became bidirectional DC-DC converters. Finally, the experimental results are provided to verify the feasibility of the proposed method. [ABSTRACT FROM AUTHOR]

This study presents a new modular switched-capacitor DC-DC converter (MSCC) which is primarily designed with fault-tolerant capability to promote low-voltage applications such as fuel cells and photovoltaics. The converter can increase a low voltage level to a high voltage level by increasing the number of modules and/or the duty ratio. The proposed topology is modular and has high scalability for a high voltage gain. Another key advantage of the converter is its fault tolerance feature with a minimum change to the duty ratio. The proposed topology is first modeled analytically and then simulated in PSIM software with new control algorithms. The circuit architecture, operating principle, voltage/current stress and fault-tolerant operations are verified by using analytical and simulation methods based on a 200-V voltage supply. Moreover, experiments are also carried out on a low-voltage DC-DC prototype converter for validating the voltage ratio, efficiency and reliability. Test results have proved the effectiveness of the proposed topology under normal and fault conditions (open circuit faults of switches and capacitors). In addition to fuel cells, the developed converter can also be applied to photovoltaics and other low-voltage DC power systems which demand high efficiency, voltage output and high reliability. [ABSTRACT FROM AUTHOR]

Conventional half‐bridge (HB) LLC converters have been a good candidate for the first stage in the two‐stage conversion structure because of its high conversion efficiency and high frequency operation ability. However, the voltage gain is only 0.5 exclusive of the transformer, resulting in the reduced efficiency for high step‐down applications. In order to solve this issue, in this paper, a novel hybrid HB LLC converter with double resonant tanks is firstly presented for high step‐down ratio applications. The distinctive features of the proposed converter are as follows: (1) the voltage gain of 0.25 is achieved by incorporating the switched capacitor circuit. Thus, the primary turns number for the transformer is halved compared with conventional HB LLC converters. Correspondingly, the smaller primary side winding losses and transformer volume can be implemented. (2) The power splitting and low input current ripple can be obtained due to the employed double resonant tanks. Thus, the uniform thermal distribution and low input filter capacitance are the second advantage for the proposed converter. (3) Soft switching over the entire operation range still can be maintained with larger magnetics inductance. The detailed operation principles, circuit analysis, and resonant tank design for the proposed converter are introduced and presented. A hardware prototype with 36–60 V input, 3 V/50 A‐output is built to demonstrate the declared features of the proposed hybrid converter. [ABSTRACT FROM AUTHOR]

This paper presents a tunable matching network for extracting maximum power from an RF energy source. The proposed matching scheme employs a three-state tuning scheme to adapt the variations in RF to DC converter (RDC) input impedance with respect to the input power. The capacitor and the inductor in the matching network are tuned dynamically using switched capacitor circuits. For realizing a tunable inductor, we propose to use a reactance compensated inductor i.e., a shunt LC network operating below its resonant frequency. The proposed scheme is realized in a standard 0.18 μm CMOS technology node, with a load resistance of 10 k Ω , and operating frequency of 953 MHz. The RDC converter with the proposed matching scheme achieves a peak power conversion efficiency (PCE) of 51% at an input power level of −12 dBm, which is 73% higher compared to an RDC with a fixed matching network designed for −24 dBm input power. The proposed matching scheme extends the input power range over which maximum power transfer takes place by 9 dBm compared to a fixed matching scheme. [ABSTRACT FROM AUTHOR]

This article proposes a real-time dynamic maximum efficiency tracking algorithm for wireless power transfer (WPT) systems with multiple receivers. The algorithm sequentially varies the net reactance of each of the receivers using switched capacitor circuits (SCCs) to reach the maximum efficiency point (MEP). The MEP in multiple-receiver systems varies in the presence of cross-coupling. This article provides an in-depth analysis of the effects of cross-coupling and proves that cross-coupling could be beneficial or detrimental to efficiency, depending on circuit conditions such as the load resistances and coupling factors among the coils. Hence, unlike previous research, this article emphasizes the improvement of the link efficiency in the presence of cross-coupling rather than the complete elimination of its effects. Experimental results have been included for a single-transmitter and two-receiver system to validate the feasibility of the proposed algorithm. [ABSTRACT FROM AUTHOR]

Integration of multilevel inverters with renewable energy sources have been the subject of many research projects. Numerous topologies of multilevel inverters have been investigated for stand-alone and grid-connected PV systems. The high number of switching devices, complexity, large size, voltage imbalance, and high cost are main drawbacks of the conventional topologies. This paper presents a new three-phase, three-port, five-level inverter based on a switched-capacitor circuit for PV applications. Compared to the conventional topologies, the proposed inverter has voltage boosting capability and multilevel operation without using clamping diodes or flying capacitors, simplifying the control algorithms and improving the reliability, efficiency, and lifetime. The presented multilevel inverter offers 25% reduction in power devices counts and 50% reduction in flying capacitors. The proposed inverter solves the capacitor voltage balancing issue of the conventional topologies and achieves the lowest voltage stress, making it suitable for high voltage applications. Additionally, the new topology harnesses the superior features of silicon-carbide devices; hence, a fast-switching speed can be employed to reduce size of the storage elements and output filter requirements. Furthermore, the soft-switching operation is realized to regulate the charging current of the capacitor. The operating principle of the proposed topology is investigated, and its properties are compared to the traditional multilevel inverters. A laboratory prototype was built to validate the effectiveness of the proposed circuit, simulation and experimental results for the proposed inverter are provided. [ABSTRACT FROM AUTHOR]

This letter proposes a switched capacitor (SC)-based continuously adjustable modular bidirectional dc–dc converter. The structure of the proposed converter consists of three types of modules, series–parallel SC converter module, regulating module, and resonant SC converters module. A basic configuration of three modules working in buck operating mode is analyzed in detail. The boost mode operation is symmetrical to the buck mode. The regulation module provides all regulation capability, and the other two modules operate at fixed duty cycle and provide the main conversion ratio. A prototype of the basic configuration was built to verify the theory. The peak efficiency of the prototype is 97.15%. [ABSTRACT FROM AUTHOR]

In this article, a new high voltage gain quasi-Z-source (QZS) dc–dc converter suitable for renewable energy applications is presented. The proposed converter utilizes a zero voltage transition auxiliary circuit with coupled inductors to provide soft-switching conditions for all switches for a wide range of output power. In addition, a switched capacitor circuit is employed to obtain a higher voltage gain and lower voltage stress. The main advantages of the proposed converter include high voltage gain, high efficiency, reduced switch and diode voltage stress, continuous input current, and common ground between the output and input, which are important features for photovoltaic applications. In this circuit, the reverse recovery problem of diodes is alleviated. Operating principles and design considerations of the proposed converter are analyzed. Moreover, to prove the validity of the theoretical analysis, a 200-W prototype of the proposed converter is implemented and the experimental results are shown. [ABSTRACT FROM AUTHOR]

A series connection of SiC MOSFETs for kV blocking capability can enable more design flexibility in modular multi-level converters as well as other topologies. In this paper, a novel gate driver circuit capable of driving series-connected SiC MOSFETs for high voltage applications is proposed. The primary advantage of the proposed design is that a single gate driver was used to switch all the series devices. The circuit used switching capacitors to sequentially charge and discharge device gate capacitances during switching and enable a negative turn-off voltage to avoid device coupling from Miller-capacitive feedback effects. With the proposed gate driver design and appropriate component values selection, avalanche breakdown due to voltage divergence during switching transients could be avoided with only a minor imbalance in the top device. Simulations and experimental measurements showed that the zero-current turn-off transition of all switches was achieved, and this approved the validity of the design. [ABSTRACT FROM AUTHOR]

This elaboration presents the concept of the design, parameters, experimental investigation, and thermal numerical model solved using the finite element method of a high-power-density DC–DC converter. The analyzed unit can be utilized as a stand-alone converter or as a module for a scalable high-voltage gain system. The converter has a decreased bill of materials since it does not use typical chokes and heatsinks. It is based on switched capacitor circuits supported by a resonant choke which protects against inrush currents. A printed circuit board is utilized not only for the resonant inductance design but also for cooling transistor and diode devices. The paper demonstrates the design concept and the achieved parameters. Experimental results show heat distribution on the printed circuit board and components in a steady state and dynamical states as well. The converter parameters and their efficiency are measured as well. The convergence of experimental results and heating simulations is demonstrated. The numerical model is used for the investigation of design cases. The printed circuit board size, thermal via pattern, and heating process during the overload of the converter are investigated. [ABSTRACT FROM AUTHOR]

A nW-level BJT-based bandgap reference with fine grained voltage and temperature coefficient trimming is presented. The bandgap reference utilizes switched capacitors (SC) as impedance elements instead of resistors in a current mode configuration. This configuration enabled low power (38nW) with a minimal area (0.0174 mm2). The voltage could be trimmed independently without affecting the temperature coefficient. The SC’s are stacked in order to achieve accurate trimming without using unrealistically small capacitors. The temperature coefficient can be trimmed between 50-200 ppm/°C in either direction, while the voltage can be trimmed between 580-800mV.

Maximum power point tracking (MPPT) plays a significant role in a photovoltaic (PV) system's optimal performance. Bypass diodes create multiple peaks on the power–voltage curve during partial shading conditions (PSCs), reducing the PVs overall power extraction capability. This article proposed a new hybridized architecture for switched inductor and switched capacitor circuit based voltage equalizer (VE) topology with reduced switch count to prevent the multiple peaks and increase the energy yield during PSCs. The proposed VE operates with a fixed duty cycle and frequency. The MPPT controller with PSC detection is also proposed to operate VE only when the PSC is detected to avoid unwanted switching and conduction losses. The proposed system's effectiveness for ten modules connected in series has been determined compared with other modular state-of-the-art VEs. The proposed topology can be extended with a smaller number of control switches. On average, the experimental results showed a 30.42% improvement in energy yield in comparison with the conventional systems. Furthermore, the proposed controller offers the MPPT efficiency of 99.28% with a tracking time of 0.10 s for uniform shaded conditions and 0.692 s for PSCs on average. [ABSTRACT FROM AUTHOR]

Recently, with the aim of extending the use of the CP in all those applications where a time-variant signal must be amplified with its DC component above the positive power supply rail, the signal amplification feature of a conventional Dickson charge pump (CP) has been investigated, introducing a small-signal model for each particular condition in which a CP can work. In this paper this idea is further investigated, especially under the slow switching limit (SSL) condition, and experimental validation has been carried out using a 65 nm CMOS technology for four different voltage gain values. Starting from an equivalent model of the CP, the main small- and large-signal parameters are analytically derived and discussed in depth. As a proof of concept, experimental measurements on four CPs with different numbers of stages confirm the validity of this unconventional application and the effectiveness of the CP when used as an amplifier. [ABSTRACT FROM AUTHOR]

This article presents a 48–1 V merged-two-stage hybrid-switched-capacitor converter with a linear extendable group operated point-of-load (LEGO-PoL) architecture for ultrahigh-current microprocessors, featuring 3-D stacked packaging and coupled inductors for miniaturized size, fast speed, and vertical power delivery. The architecture is highly modular and scalable. The switched-capacitor circuits are connected in series on the input side to split the high input voltage into multiple stacked voltage domains. The multiphase buck circuits are connected in parallel to distribute the high output current into multiple parallel current paths. It leverages the advantages of switched-capacitor circuits and multiphase buck circuits to achieve soft charging, current sharing, and voltage balancing. The inductors of the multiphase buck converters are used as current sources to soft-charge and soft-switch the switched-capacitor circuits, and the switched-capacitor circuits are utilized to ensure current sharing among the multiphase buck circuits. A 780-A vertical stacked CPU voltage regulator with a peak efficiency of 91.1% and a full load efficiency of 79.2% at an output voltage of 1 V with liquid cooling is built and tested. The switched capacitor circuits operate at 286 kHz and the buck circuits operate at 1 MHz. It regulates output voltage between 0.8 and 1.5 V through the entire 780-A current range. This is the first demonstration of a 48–1 V CPU voltage regulator to achieve over 1-A/mm $^\text{2}$ current density and the first to achieve 1000-W/in $^3$ power density. [ABSTRACT FROM AUTHOR]

Ring amplifiers enable efficient amplification with less power consumption. These are characterized by fairly power requirements, and innate rail-to-rail output swing and are robust against PVT variations. In this paper, we are presenting an improved self-biased anti-series diode-based ring amplifier (ASD-RAMP) design, implemented on 45-nm CMOS technology. The design uses two diode-connected PMOS transistors that are connected in an anti-series manner to generate a large resistance because of which a high dead-zone voltage is generated. The ASD-RAMP has a settling time of only 4.05 ns, which is nearly half of the conventional self-biased ring amplifier (CSB-RAMP). In comparison to CSB-RAMP, the proposed ASD-RAMP improves the dead-zone voltage by 1. 1 × while requiring 6.76% less power. The circuit is durable and suitable for high-performance applications since it exhibits great resilience to PVT variations in addition to the improved dead zone voltage and reduced settling time. • Anti-Series Diode arrangement based ring amplifier is proposed to improve the dead zone voltage and the settling time. • RC electrical equivalent model for the settling time analysis of the circuit. • Proposed ring amplifier circuit is robust against the PVT variations. [ABSTRACT FROM AUTHOR]

By using a single dc voltage source to feed a 4-level switched-capacitor (SC) unit and a 3-level NPP/NPC unit simultaneously, a new 9-level inverter is developed in this work. The 4-level unit is implemented by cascading an inverting half-bridge with a double- or half-mode SC circuit. It involves four transistors, two diodes and two capacitors with self-balanced voltage. Inrush charging current variation di/dt of capacitors at switching instants is successfully suppressed by inserting a small inductor into the SC unit. Compared with the existing solutions for 9-level inverters, the proposed circuit has the advantages of simpler structure and lower cost per level. These make the proposed inverter very suitable for low voltage applications such as PV and fuel cells. Circuit configuration, operation, system characteristics under POD-PWM modulation are analyzed in detail. Feasibility and dynamic performance are also demonstrated experimentally.

The conventional neutral point clamped (NPC) multilevel inverter topology needs voltage balancing circuits to balance the dc-link capacitor, the number of component count is high and output voltage is half of the input voltage which increase the size of the source side dc/dc converter in PV applications. In this paper, a new topology of seven level neutral point clamped inverter is developed. The proposed inverter has a self-voltage boosting capability using a floating capacitor to boost the output voltage one and half of the input voltage. In this proposed topology, no additional sensors are required for the floating capacitor voltage stability, which results in minimizing the complexity of designing the inverter. The direct link between the neutral point and the mid-point of the dc-link capacitors significantly reduces the leakage current and common mode voltage in this inverter. A thorough comparison between the developed topology and recent suggested topologies is carried out which set the benchmark for the proposed one due to its lower switch count and higher voltage gain. The proposed topology is verified in simulation and prototype hardware model and results are discussed with dynamic load variations. The efficiency of the inverter is 97.1% @200W and low as 88.1 % @ inductive load. The voltage THD is 17.01% for simulation and 19.3% I for experimental is results.

In this article, a novel single-switch, high step-up dc–dc converter based on three-winding coupled inductor and voltage multiplier circuit (VMC) is proposed. And on this basis, pump capacitor unit (PCU) is integrated to achieve a very high voltage gain. The converter makes full use of the advantages of three-winding coupled inductor, skillfully combines it with the VMC, and integrates the PCU that can be used in superposition to further improve the voltage gain. The voltage stress of the switch is reduced by using a passive clamping circuit to recycle the leakage energy of the coupled inductor. The operating principle and steady-state analysis of the presented converter in continuous conduction mode are introduced in detail. Moreover, the comparative analysis shows that under the same conditions, the proposed converter has higher voltage gain and lower voltage stress than others. Several advantages include high voltage gain, low voltage stress, low turns ratio of coupled inductor, and high conversion efficiency, make the proposed converter very suitable for new energy generation applications, such as photovoltaic systems. Finally, the feasibility of the proposed converter and the correctness of theoretical analysis are verified by a 500-W prototype at 50 kHz switching frequency. [ABSTRACT FROM AUTHOR]

Scaling is one of the most important aspects and is considered for designing digital circuits. With the help of scaling techniques, it can integrate more features into the chip for optimization of actual circuit space. But the main drawback of this scaling is short channel effects. And also as the technology shrinks, the leakage power plays a crucial role compared to dynamic power consumption. To avoid leakage power, the proposed design technology is used for the optimization of power and for avoiding short channel effects. To further reduce power consumption, the CMOS technology is replaced with transmission gates in switched-capacitor converter circuits and GDI Technique while generating clock signals in the circuit for operations. [ABSTRACT FROM AUTHOR]

This work proposes a new OLED driver architecture with 10-bit segmented DAC and switched capacitor multiply-by-two circuit application. A 30-channel 10-bit switched capacitor driver chip prototype is implemented in 0.18- μ m CMOS technology. In this architecture, the achieved output range is 1.5–4.8 V for an input range of 1.5–3.15 V, which is suitable for OLED driver with different colors. This architecture is not only converting the digital input signal to analog output for the display panel but also giving amplified high output voltage range. In the segmented DAC, 6-bit coarse DAC and 4-bit fine DAC are used for the input voltage range 1.5–3.15 V. In a conventional RDAC for the output voltage of 4.8 V, it requires 2 1 4 switches i.e., 14-bit RDAC for the same resolution. Hence, conventional RDAC driver is four times larger than the proposed innovative very compact and high speed 10-bit segmented DAC switched capacitor OLED driver. The new architecture drastically reduces the number of switches and complex metal routing which results in reduced power consumption and good settling time. In the proposed OLED driver, no extra buffer is required as switched capacitor op-amp is applied for the same purpose with a gain of more than one. This high-resolution design with small die area also improves the linearity and uniformity with low-power consumption. The post-simulated results show that the OLED driver exhibits the maximum DNL and INL of 0.03 LSB and − 0.06 LSB, respectively, with an LSB voltage of 3 mV. The one-channel area is 0.586 mm × 0.017 mm and the settling time is 4.25 μ s for 30 k Ω and 30 pF driving load. [ABSTRACT FROM AUTHOR]

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This paper presents a novel light emitting diode (LED) sink driver with a high voltage gain for LED-based lighting applications. Unlike conventional LED sink drivers, the proposed driver has the nested switched-inductor/switched capacitor (SI/SC) topology consisting of an SI buck-boost converter block and a nesting-type SC cell. Owing to the nested SI/SC topology, the proposed driver offers not only a high voltage gain but also a flexible controllability of the LED currents and transformer-less structure. The effectiveness of the proposed driver is justified by some simulation results in SPICE software environment and laboratory experimental tests. In the performed simulations, the proposed driver in comparison of conventional drivers improved almost 6% power efficiency when the output power was 500 mW. Furthermore, in the performed experiments, the feasibility of the proposed topology is confirmed by demonstrating a high voltage gain and the output controllability.

The Metacapacitors project aims to improve efficiency, functionality and form factor of offline power converters suitable for LED solid-state lighting, with a view to developing an attractive technology platform for load management and power conversion across a broad range of applications. Based on integrated switched-capacitor (SC) topologies, the project adopts an integrated approach from materials to devices to circuits. We designed capacitors based on high-κ dielectric nanocrystals, that can be prepared using high-throughput microfabrication/ nanotechnology techniques, ink deposition and multilayering. The capacitor dielectric, a nanocomposite composed of (Ba, Sr)TiO3 nanocrystals in polyfurfuryl alcohol (BST/PFA, κ > 20, 100Hz-1 MHz, loss < 0.01, 20 kHz), targets a high volumetric capacitance density and ripple current capability. The Dielectric is demonstrated to function in a finished capacitor >1000 h at 125°C. The capacitors were board integrated with a custom hybrid-switched-capacitor-resonant dc-dc converter IC. The converter integrates a balanced SC front-end with a series resonant tank, enabling nearly lossless current regulation and tranformerless galvanic isolation. The converter IC can be stacked in the voltage domain to interface a range of inputs. The tested driver delivers about 15 Wat 470 mA to a string of 12 LEDs with 90% peak efficiency.

We report on the development, installation, and operation of the first three of seven stations deployed at the ARIANNA site's pilot Hexagonal Radio Array (HRA) in Antarctica. The primary goal of the ARIANNA project is to observe ultrahigh energy (> 100PeV) cosmogenic neutrino signatures using a large array of autonomous stations, each 1 km apart on the surface of the Ross Ice Shelf. Sensing radio emissions of 100 MHz to 1 GHz, each station in the array contains RF antennas, amplifiers, 1.92 G-sample/s, 850 MHz bandwidth signal acquisition circuitry, pattern-matching trigger capabilities, an embedded CPU, 32 GB of solid-state data storage, and long-distance wireless and satellite communications. Power is provided by the sun and buffered in LiFePO4 storage batteries, and each station consumes an average of 7 W of power. Operation on solar power has resulted in ≥58% per calendar-year live-time. The station's pattern-trigger capabilities reduce the trigger rates to a few milli-Hertz with 4-sigma voltage thresholds while retaining good stability and high efficiency for neutrino signals. The timing resolution of the station has been found to be 0.049 ns, RMS, and the angular precision of event reconstructions of signals bounced off of the sea-ice interface of the Ross Ice Shelf ranged from 0.14 to 0.17°.

The tunneling magnetoresistance (TMR) with high-resolution digital output is widely used in military and civil fields. In this work we proposed a low-noise read-out circuit and a four-order fully differential sigma-delta modulator for TMR sensors. In the read-out circuit, we used symmetrical cascade for good matching. We used correlated double sampling (CDS) technique to improve the conversion accuracy of the modulator. In switched capacitor circuits we used time-division multiplexing to suppress charge injection and clock feedthrough. The high-precision application specific integrated circuit (ASIC) chip was fabricated by a 0.35 μ m CMOS process from Shanghai Huahong foundry. The TMR sensor was placed in an environment of three-layer magnetic shielding for test. The active area of the ASIC is only about 3   mm × 3   mm. At a sampling frequency of 20 kHz, the TMR magnetometer consumes 77 mW from a single 5 V supply; the sigma-delta modulator for TMR can achieve an average noise floor of −141 dBV. The magnetometer works at a full scale (FS) of ± 1 0 0   μ T , it can achieve a nonlinearity of 0.2% FS and a resolution of 0.15 nT/Hz 1 / 2 over a signal bandwidth. [ABSTRACT FROM AUTHOR]

In this article, a single‐stage bridgeless LLC resonant converter with a constant frequency control method is proposed for a high‐brightness light‐emitting diode (LED) driver. LED strings require drivers with high power density and high efficiency. This article presents a novel LED driver circuit topology based on switch integration and the switching controlled capacitor (SCC) technique. By combining the merits of a totem‐pole bridgeless boost PFC unit and a high frequency SCC‐LLC half‐bridge resonant converter, the proposed topology can achieve high efficiency. Due to the SCC‐LLC circuit topology structure, constant frequency control of the LLC resonant converter is achieved by the regulation of the equivalent resonant capacitance. The proposed novel LED driver topology can automatically achieve soft‐switching characteristics and a high power factor. The operating principle of different operation modes and the characteristics of the proposed LED driver are analysed in detail. Finally, to demonstrate the feature of the proposed topology, a 100 W/70 V laboratory prototype is built. The satisfactory experimental results correspond with the theoretical analysis and parameter design. [ABSTRACT FROM AUTHOR]

In this paper, a novel voltage equalization technique based on the hybridization of total cross-tied configuration and switching capacitor concept for enhancing the power generation of PV arrays during partial shading is proposed. The technique uses the charge balancing concept to maintain the voltage ratio between the total cross-tied array modules and ensures higher power output and convex power curves during partial shading. The validation of the proposed system is carried out in the MATLAB environment for three different size PV arrays under partial shading and compared with the conventional and three reconfiguration techniques in terms of power generation, losses, and conversion efficiency. Also, the insertion losses encountered by the proposed system are derived mathematically. The study concludes that the proposed system tends to generate higher power than any other techniques during shading with conversion efficiency of more than 97%. [ABSTRACT FROM AUTHOR]

Figures-of-Merit (FOMs) are widely-used to compare power semiconductor materials and devices and to motivate research and development of new technology nodes. These material- and device-specific FOMs, however, fail to directly translate into quantifiable performance in a specific power electronics application. Here, we combine device performance with specific bridge-leg topologies to propose the extended FOM, or X-FOM, a Figure-of-Merit that quantifies bridge-leg performance in multi-level (ML) topologies and supports the quantitative comparison and optimization of topologies and power devices. To arrive at the proposed X-FOM, we revisit the fundamental scaling laws of the on-state resistance and output capacitance of power semiconductors to first propose a revised device-level semiconductor Figure-of-Merit (D-FOM). The D-FOM is then generalized to a multi-level topology with an arbitrary number of levels, output power, and input voltage, resulting in the X-FOM that quantitatively compares hard-switched semiconductor stage losses and filter stage requirements across different bridge-leg structures and numbers of levels, identifies the maximum achievable efficiency of the semiconductor stage, and determines the loss-optimal combination of semiconductor die area and switching frequency. To validate the new X-FOM and showcase its utility, we perform a case study on candidate bridge-leg structures for a three-phase 10 kW photovoltaic (PV) inverter, with the X-FOM showing that (a) the minimum hard-switching losses are an accurate approximation to predict the theoretically maximum achievable efficiency and relative performance between bridge-legs and (b) the 3-level bridge-leg outperforms the 2-level configuration, despite utilizing a SiC MOSFET with a lower D-FOM than in the 2-level case.

A new dual-input DC-DC converter based on quasi-Z source converter is proposed in this study. This converter is a suitable option for efficiently interfacing two energy sources with a common load. The proposed topology, by integrating the switched-capacitor cell and coupled-inductor, provides a high step-up gain of voltage conversion at small duty cycles. This topology works only by two switches and voltage stress across the switches is low. Furthermore, continuous input current is one of the key features of the proposed converter which makes it suitable for hybrid photovoltaic and fuel cell systems. In this research, it is attempted to explain the operating principles, steady-state analysis, control and modulation for the proposed converter under continuous inductor current mode. The merits of the proposed converter are presented compared with those of other dual-input converters. Finally, simulation results from MATLAB\Simulink are presented and experiments with a 150W prototype are performed to investigate the performance and effectiveness of the studied circuit.

This article proposes a fully dynamic, low-power, wideband, time-interleaved (TI), noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) based on the cascade of integrators with feedforward (CIFF) architecture. Both the interleaving operation and the loop filter are implemented by using the fully passive switched-capacitor circuits. The feedforward summation is realized by a multi-path dynamic comparator. The overall noise transfer function (NTF) is highly robust against process, voltage, and temperature (PVT) variations since the NTF is determined by device ratios. This allows the NTF zeros to be close to 1, with a good NS effect. Compared with a recently published TI NS SAR based on the error-feedback (EF) architecture, this work does not need a static amplifier, thus leading to the fully dynamic operation. Meanwhile, it eliminates the dependence of NTF on the PVT-sensitive amplifier gain. Implemented in a 40-nm CMOS process, the prototype ADC achieves an SNDR of 69.1 dB, a bandwidth of 50 MHz, and a power consumption of 8.5 mW under a 1.1-V supply, leading to a Walden FoM of 36.3 fJ/conv.-step. [ABSTRACT FROM AUTHOR]

This article presents a method for modifying an electrostatic harvester (EH) to allow autonomous management of its charge. The method involves segmenting a naturally antagonistic (out-of-phase) EH and connecting it with diodes to form an integrated self priming circuit (I-SPC). A model for the I-SPC is presented and shown that an exponential increase in voltage on the EH will occur over 10's of harvesting cycles. Furthermore, the model finds that increasing the segmentation of the EH allows harvesting at lower capacitance change ratios. The model is validated through simulation and experiment. The experiment is performed using a dielectric elastomer EH which consists of eight segments. During experimentation, it is confirmed that an I-SPC charged to 5 V is capable of reaching a voltage of approximately 2600 V after 40 capacitance change cycles. This fast voltage gain highlights the possibilities of self-managed EHs which harvest renewable kinetic energy autonomously to power wireless sensor networks (WSNs). The lack of maintenance associated with these systems will allow cheap WSN powered by renewable energy sources to be implemented in industrial applications. [ABSTRACT FROM AUTHOR]