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Ternary content-addressable memories (TCAMs) can perform high-speed and deterministic table lookups. However, its main drawback is high power consumption. A significant portion of the TCAM power is consumed by match-line sense amplifiers (MLSAs) for match detection. This paper presents a 20-kilobit TCAM featuring two MLSAs with positive-feedback techniques. The proposed circuits have been fabricated on a test chip in 0.18-[micro]m CMOS technology. Energy measurement results of the two MLSAs show reductions of 56% and 48%, respectively, over the conventional current-race MLSA. Index Terms--Associative memories, content-addressable memory, feedback circuits, match-line sense amplifiers (MLSAs).

This paper presents a 5-Gb/s clock and data recovery (CDR) circuit which implements a calibration circuit to correct static phase offsets in a linear phase detector. Static phase offsets directly reduce the performance of CDR circuits as the incoming data is not sampled at the center of the eye. Process nonidealities can cause static phase offsets in linear phase detectors by adversely affecting the circuits in a way which is difficult to design for, making calibration an attractive solution. Both the calibration algorithm and test chip implementation are described and measured results are presented. The CDR circuit was fabricated in a 0.18-[micro]m, six metal layer standard CMOS process. With a pseudorandom bit sequence of [2.sup.7] - 1 calibration improved the measured bit error rate from 4.6 x [10.sup.-2] to less than [10.sup.-13]. Index Terms--Calibration, clock and data recovery (CDR), CMOS circuits, ring oscillator.

Burn-in is a quality improvement procedure challenged by the high leakage currents that are rapidly increasing with IC technology scaling. These currents are expected to increase even more under the new burn-in environments leading to higher junction temperatures, possible thermal runaway, and yield loss during burn-in. The authors estimate the increase in junction temperature with technology scaling. Their research shows that under normal operating conditions, the junction temperature is increasing 1.45X/generation. The increase in junction temperature under the burn-in condition was found to be exponential. The range of optimal burn-in voltage and temperature is reduced significantly with technology scaling. Index Terms--Burn-in testing, CMOS technology scaling, junction temperature, thermal management.

A new method for deriving an equation for the oscillation frequency of a ring oscillator is proposed. The method is general enough to be used for a variety of types of delay stages. Furthermore, it provides a framework to include various parasitic and secondary effects. The method is used to derive an equation for a common ring oscillator topology. The validity of the method and the resulting equation have been verified through simulation. The oscillation frequencies predicted by the proposed method are more accurate than existing equations and account for more secondary effects. Index Terms--CMOS analog integrated circuits, equations, high-speed integrated circuits, voltage-controlled oscillators.

In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal-oxide-semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35-[micro] m CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield. Index Terms--Band-to-band tunneling, CMOS ICs reliability, gate-induced leakage current, standard logic cells layout.