25 results on '"Saeidi, Roghayeh"'
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2. A low-power low-offset charge-sharing technique for double-tail comparators
3. A low-power dynamic comparator for low-offset applications
4. Highly stable, low power FinFET SRAM cells with exploiting dynamic back-gate biasing
5. An ultra low-power DAC with fixed output common mode voltage
6. Accurate and Insightful Closed-Form Prediction of Subthreshold SRAM Hold Failure Rate
7. KAZE-SAR: SAR Image Registration Using KAZE Detector and Modified SURF Descriptor for Tackling Speckle Noise
8. SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6–3.6-μW/DMIPS 40–80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode
9. SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management
10. An Analysis of Stepwise Adiabatic Circuits
11. SRAM Security and Vulnerability To Hardware Trojan: Design Considerations
12. An Ultra Low-power Low-offset Double-tail Comparator
13. A Reduced Store/Restore Energy MRAM-Based SRAM Cell for a Non-Volatile Dynamically Reconfigurable FPGA
14. Hardware Trojan Prevention and Detection by Filling Unused Space Using Shift registers, Gate-chain and Extra Routing.
15. Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs
16. A Novel Sensing Circuit with Large Sensing Margin for Embedded Spin-Transfer Torque MRAMs
17. SRAM hardware Trojan
18. Secure FPGA Design by Filling Unused Spaces.
19. Low power and roboust FinFET SRAM cell using independent gate control
20. Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell
21. A Subthreshold Symmetric SRAM Cell With High Read Stability
22. A subthreshold dynamic read SRAM (DRSRAM) based on dynamic stability criteria
23. A 32kb 90nm 9T-cell sub-threshold SRAM with improved read and write SNM.
24. A novel low power 8T-cell sub-threshold SRAM with improved read-SNM.
25. Noise reduction of consecutive images using a new adaptive weighted averaging filter
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