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This research article examines a L‐shaped dielectrically modulated label free TFET (L‐DM‐TFET) biosensor for the purpose of detecting different biomolecules using a label‐free biosensing detection technique. The proposed structure allows for the recognition of biomolecules by modulating various electrical properties, such as the drain current, transconductance, and linearity parameters. The source region of the proposed TFET incorporates a SiGe (source)/Si (channel) heterojunction, utilizing a low bandgap material of SiGe. This heterojunction is employed to enhance the ON‐state current of the devices. The materials used and the fabrication steps involved in our proposed device are compatible with complementary metal‐oxide‐semiconductor (CMOS) technology. This analysis is conducted using a calibrated Silvaco technology computer‐aided design (TCAD) simulator. Additionally, by considering a dielectric constant range of 1–12, we calculate various figure of merits (FOMs) parameters for the device. These include evaluation of linearity, sensitivity, and noise characteristics. Furthermore, we have conducted an analysis of linearity FOMs, such as VIP2, VIP3, IIP3, and IMD3 for the proposed device under study. Additionally, the linearity analysis of the presented tunneling FET (TFET) indicates the device's excellent performance in distortionless switching operations. Consequently, the L‐shaped dielectrically modulated biosensor holds potential suitability for high‐speed circuit designs. [ABSTRACT FROM AUTHOR]

In this paper, we systematically examined the impact of fin height ( H\mathrm{ Fin} ) and fin angle ( \theta \mathrm{ Fin} ) on the ac performance parameters including total gate capacitance ( C\mathrm{ gg} ), RC delay ( C_{\mathrm{ gg}}V_{\mathrm{ DD}}/I_{\mathrm{\scriptscriptstyle ON}} ), cutoff frequency ( f_{T} ), energy ( E ), total power ( P_{\mathrm{ Total}} ), and leakage power ( P_{\mathrm{ Leakage}} ) of hybrid FinFETs at the supply voltage, V\mathrm{ DD} with on-current I\mathrm{\scriptscriptstyle ON} . The RC delay, energy, and total power consumption are the primary factors limiting the operating frequency of the high-performance devices. Therefore, these electrical parameters are needed to be addressed in the architectural level of the fin based devices. In this paper, a calibrated numerical device simulation tool is used to achieve the best device performances of 14-nm hybrid FinFETs. From the simulated current–voltage ( I – V ) and capacitance–voltage ( C – C\mathrm{ gg}V\mathrm{ DD}/I\mathrm{\scriptscriptstyle ON} , fT , CV2, P\mathrm{ Total} , and P\mathrm{ Leakage} are extracted to analyze the effect of H\mathrm{ Fin} and \theta \mathrm{ Fin} on the performance matrices of these devices. In addition, this paper proposes an optimum structural configuration for 14-nm hybrid FinFET architecture for digital application perspective. [ABSTRACT FROM AUTHOR]